DiLab - User contributions [en]

OpenLane 2

2026-07-03T20:27:18Z

Leo: /* Usecase: SRAM integration for IHP-Open-PDK */

{{TocRight}}
OpenLane versions 1 and 2 is the VLSI design flow management framework.

However, it has been superseeded by [[LibreLane]] that is suggested for new designs.

= Setup Openline2 =
9https://openlane2.readthedocs.io/en/latest/getting_started/installation_overview.html The advised path]
is to setup NIX environment and then run openline2 from there, rather than using a dockerized version.

== Install Nix ==
Set up the Nix environment:
sudo apt-get install -y curl

curl --proto '=https' --tlsv1.2 -sSf -L https://install.determinate.systems/nix | sh -s -- install --no-confirm --extra-conf "
extra-substituters = https://openlane.cachix.org
extra-trusted-public-keys = openlane.cachix.org-1:qqdwh+QMNGmZAuyeQJTH9ErW57OWSvdtuwfBKdS254E=
"
Make sure to close all terminals after you’re done with this step.

=== If have Nix already ===

nix-env -f "<nixpkgs>" -iA cachix
sudo env PATH="$PATH" cachix use openlane
sudo pkill nix-daemon

== Install OpenLane 2 after Nix ==

git clone https://github.com/efabless/openlane2
nix-shell
openlane --smoke-test

== Other tools ==
There are many other tools you could setup separately, just know that openlane2 expects and is sensitive to the versions of the tools, and may not work if your tool is older or newer.

= My local setup =
This is how I use the Openlane2 tools after the setup.

One important note is that they generate MANY intermediate and log files in the "runs" directory under your project, every time you run openlane. This may take 6GB and more of the disk space for every run.

Usually my project is mapped to a cloud drive such as Dropbox, and spamming it with tons of files may create confusion when receiving an email later that someone has deleted 2000+ files from your account. Therefore I do the runs locally, possibly outside the project directory.
To achieve that, I run the following commands:

cd git.local/openlane2
nix-shell
openlane --smoke_test # Sanity test for the tools (optional)
cd your/project/

run_openlane_local.sh config.json # will save run logs under work.local/... (recommended)
or
opennlane config.json # will save the run logs in the project directory work/... (cloud?!)

= Setting up a new project =
A project is usually kept in one directory. It may contain:
* config.json file with the project options. Potentially you could have several configs, for different technologies, although probably berret to have a separate project for each.
* src/ directory with the Verilog or VHDL files
* runs/ directory with many intermediate and log files as populated by the openlane2 tool(s).
** The runs/ has a RUN<timestamp> folder for each openalne run. Each of those will have the following:
*** Folders from 01-... and up to 74-... or more with files according to the respective run steps
*** final/ directory with the final results, including the magic and klayout and gds files with the final layout, spice files, etc.
*** tmp - temporary directory.
*** flow, warning and error logs.

== The config.json file ==
Technically other formats such as yaml are also supported, but lets stick to json.
Here is an example of a simple config.json file for SKY PDK:
{
"DESIGN_NAME": "counter",
"VERILOG_FILES": ["src/counter.v"],
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"FP_CORE_UTIL": 40,
"RT_MAX_LAYER": "met4"
}

Here is another for IHP PDK:
{
"DESIGN_NAME": "counter",
"VERILOG_FILES": ["src/counter.v"],
"PDK": "sg13g2",
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"FP_CORE_UTIL": 40,
"RT_MAX_LAYER": "Metal4"
}
Here is a bit more with the die area:
{
"DESIGN_NAME": "adder_16bit",
"VERILOG_FILES": "dir::src/adder_16bit.v",
"CLOCK_TREE_SYNTH": false,
"CLOCK_PORT": null,
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 100 100",
"PL_TARGET_DENSITY": 0.65,
"VDD_NETS": ["vccd1"],
"GND_NETS": ["vssd1"],
"DIODE_INSERTION_STRATEGY": 4
}

= Usecase: Adder =
This is logic only, no registers

config.json
{
"DESIGN_NAME": "adder_16bit",
"VERILOG_FILES": "dir::src/adder_16bit.v",
"CLOCK_TREE_SYNTH": false,
"CLOCK_PORT": null,
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 100 100",
"PL_TARGET_DENSITY": 0.65,
"VDD_NETS": ["vccd1"],
"GND_NETS": ["vssd1"],
"DIODE_INSERTION_STRATEGY": 4
}

Verilog source (src/adder_16bit.v):
`default_nettype none
module adder_16bit (
input wire [15:0] a,
input wire [15:0] b,
input wire cin,
output wire [15:0] sum,
output wire cout
);
assign {cout, sum} = a + b + cin;
endmodule

= Usecase: Simple counter =
This design has a few registers

config.json
{
"DESIGN_NAME": "counter",
"VERILOG_FILES": ["src/counter.v"],
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"FP_CORE_UTIL": 40,
"RT_MAX_LAYER": "met4"
}

Verilog source (counter.v):
module counter (
input wire clk,
input wire reset,
output reg [15:0] count
);
always @(posedge clk or posedge reset) begin
if (reset)
count <= 16'b0;
else
count <= count + 1'b1;
end
endmodule

= Usecase: NeoRV32 MCU =

NeoRV32 is an open source MCU with many peripheral options written in VHDL.

* [https://github.com/stnolting/neorv32 GitHub repo] - Original VHDL version
* [https://github.com/stnolting/neorv32-verilog Repo for the verilog version] - A wrapper and converter script for Verilog

==== VHDL to Verilog ====
Openlane2 is using Yosis for synthesis, which natively supports Verilog.
Therefore we need to convert to a flat Verilog file. Therefore clone the second repository recursively:
git clone --recursive -j8 git@github.com:stnolting/neorv32-verilog.git
cd neorv32-verilog

Before the convertion go to the VHDL file and enable/disable the features you want.
Consider agressively disabling and downsizing everything to the minimum at least for the first runs so that the tools (e.g. yosys) can handle such a massive flat file.

cd git.local/neorv32-verilog/src/
edit* neorv32_verilog_wrapper.vhd

Go towards the end of the file and change true and false appropriately. Look for lines below the:
architecture neorv32_verilog_wrapper_rtl of neorv32_verilog_wrapper is
begin
...
generic map ( -- [note] add configuration options as required

Consider the following:
* "false" every "true" except as below
-- Internal Instruction memory (IMEM) --
IMEM_EN => true, -- implement processor-internal instruction memory
IMEM_SIZE => 16*16, -- size of processor-internal instruction memory in bytes
-- Internal Data memory (DMEM) --
DMEM_EN => true, -- implement processor-internal data memory
DMEM_SIZE => 8*32, -- size of processor-internal data memory in bytes
-- CPU Caches --
ICACHE_EN => true, -- implement instruction cache (i-cache)
ICACHE_NUM_BLOCKS => 4, -- i-cache: number of blocks (min 1), has to be a power of 2
DCACHE_EN => true, -- implement data cache (d-cache)
DCACHE_NUM_BLOCKS => 4, -- d-cache: number of blocks (min 1), has to be a power of 2
CACHE_BLOCK_SIZE => 64, -- i-cache/d-cache: block size in bytes (min 4), has to be a power of 2
...
IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
...
IO_PWM_NUM => 0, -- number of PWM channels to implement (0..32)

Install the ghdl for conversion unless already installed, and start the conversion process. Move the Verilog file to your project sourde directory when done:
sudo apt-get install ghdl
make check
make convert
mv src/neorv32_verilog_wrapper.v <your-project-dir>/src/

==== config.json ====
Some comments about the config file:
* Make sure to edit the vhdl and enable/disable only the components that you need. Or the tools may crash even with extra stack size on such a large flat file.
* "RUN_LINTER": false - othrvise here be errors on such a large flat file.
* You may need to specify a lot of size on the die:
"FP_SIZING": "absolute",
"DIE_AREA": [0, 0, 1000, 1000],
"CORE_AREA": [15, 15, 985, 985]
* Alternatively let the tools decide the size:
"FP_SIZING": "relative",
"FP_CORE_UTIL": 35,

The config.json file:
{
"DESIGN_NAME": "neorv32_verilog_wrapper",
"VERILOG_FILES": [
"dir::src/neorv32_verilog_wrapper.v"
],
"CLOCK_PORT": "clk_i",
"CLOCK_PERIOD": 25.0,
"PDK": "sky130A",
"STD_CELL_LIBRARY": "sky130_fd_sc_hd",
"FP_SIZING": "relative",
"FP_CORE_UTIL": 35,
"PL_TARGET_DENSITY_PCT": 40,
"SYNTH_STRATEGY": "AREA 0",
"VDD_NETS": [
"vccd1"
],
"GND_NETS": [
"vssd1"
],
"RUN_ANTENNA_REPAIR": true,
"RUN_HEURISTIC_DIODE_INSERTION": true,
"RUN_LINTER": false,

"_comment":
{
"FP_SIZING": "absolute",
"DIE_AREA": [0, 0, 1000, 1000],
"CORE_AREA": [15, 15, 985, 985]
}
}

==== Expected results ====
If all goes well, after an hour or so you may see the final remarks of the design in the terminal before it finishes.
A few important bits there:
#. DRC & LVS (Passed ✅)
#** DRC (Design Rule Check): The geometry of your standard cells, power straps, and routing wires strictly obeys the Sky130 foundry's physical manufacturing rules (minimum spacing, width, etc.).
#** LVS (Layout vs. Schematic): The final geometric layout perfectly matches your synthesized Verilog netlist. No unexpected shorts or open circuits were created during routing.
#. Antenna Violations (Failed 𐄂 - 8 Violations)
#* During plasma etching in fabrication, long metal wires act like antennas, collecting electrostatic charge that can blow out the thin gate oxides of connected transistors.
#* OpenLane attempted to fix these automatically (since we enabled RUN_ANTENNA_REPAIR), usually by jumping to higher metal layers or inserting "tie-down" diodes near the gates.
#* 8 violations simply mean a few nets are still too long relative to their connected gate area. In a real tape-out, you would manually inspect these in the GUI and force diode insertion or add routing blockages.
#. Max Slew & Max Cap Violations (Warnings)
#* These are electrical rule violations indicating that some signals are transitioning too slowly (slew) or driving too much load (capacitance).
#* Because we relied on OpenLane's generic fallback constraints rather than providing a custom .sdc (Synopsys Design Constraints) file, the timing-driven routing and buffer insertion heuristics were not strictly optimized for your specific 25ns clock period across all extreme temperature/voltage corners.
#* For a functional test run, these are completely safe to ignore.

==== OpenROAD ====
Now it is time to look at the generated layout.

# Force software-based OpenGL rendering
export LIBGL_ALWAYS_SOFTWARE=1

# Force Qt to use the X11 backend (bypassing native Wayland issues)
export QT_QPA_PLATFORM=xcb

openroad -gui

Then from the TCL commands console at the bottom of the OpenROAD GUI open your new design:
read_db runs/RUN_.../final/odb/neorv32_verilog_wrapper.odb

There in the tool you can proceed to the Display Control panel on the left to hide standard cells and inspect the routing layers.
* Under the Visibility tab, uncheck Instances (or specifically StdCells) to hide the internal logic gates.
* Expand the Layers menu. Here, you can toggle individual routing layers (met1, met2, met3, met4, met5) and vias to visually trace the physical connections across the die.

To jump directly to the physical wires that caused the antenna failures:
* In the top menu bar, navigate to Tools -> DRC Viewer.
* Click Load and navigate to the antenna report generated during your run.
You may need to look for the report file:
find runs/RUN_... -name "antenna.rpt"
This may find several reports. look for the latest one by OpenROAD:
runs/RUN_.../34-openroad-globalrouting/antenna.rpt
runs/RUN_.../37-odb-heuristicdiodeinsertion/3-openroad-globalrouting/antenna.rpt
runs/RUN_.../35-openroad-checkantennas/reports/antenna.rpt
runs/RUN_.../38-openroad-repairantennas/2-openroad-checkantennas/reports/antenna.rpt
runs/RUN_.../42-openroad-checkantennas-1/reports/antenna.rpt

Use the latest report by OpenROAD to open in the tool.
* The DRC Viewer will open a list of the violations, if any.
* Click on any violation in the list. The main camera will instantly pan, zoom, and highlight the exact wire segment and layer where the charge accumulation risk occurs.

= Usecase: SRAM integration for SKY (unfinished) =
Note, this design may still have unresolved issues (FIXME).
The magic tool has some issues with the sram implementation, therefore there are a few workarounds in the config file to depend mostly on klayout for the final steps.

==== config.json ====
{
"DESIGN_NAME": "top_module",
"VERILOG_FILES": [
"dir::src/top_module.v"
],
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,

"FP_SIZING": "absolute",
"DIE_AREA": [0.0, 0.0, 1000.0, 1000.0],

"VDD_NETS": ["vccd1"],
"GND_NETS": ["vssd1"],
"PDN_MACRO_CONNECTIONS": [
"sram_inst vccd1 vssd1 vccd1 vssd1"
],

"PRIMARY_GDSII_STREAMOUT_TOOL": "klayout",
"RUN_KLAYOUT_XOR": false,
"RUN_MAGIC_STREAMOUT": false,
"RUN_MAGIC_DRC": false,
"MAGIC_EXT_USE_GDS": false,
"MAGIC_INCLUDE_GDS_POINTERS": false,

"MACROS": {
"sky130_sram_1kbyte_1rw1r_32x256_8": {
"instances": {
"sram_inst": {
"location": [200.0, 200.0],
"orientation": "R0"
}
},
"vh": [
"dir::src/sram_macro.v"
],
"lef": [
"dir::macro/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
],
"gds": [
"dir::macro/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
],
"lib": {
"*": [
"dir::macro/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib"
]
}
}
}
}

==== Sources: src/ ====

top_module.v

module top_module (
// `ifdef USE_POWER_PINS
// inout vccd1,
// inout vssd1,
// `endif
input clk,
input rst_n,
input req,
input we,
input [7:0] addr,
input [31:0] data_in,
output reg [31:0] data_out,
output reg ready
);

wire [31:0] sram_dout;

// SRAM macro instantiation
sky130_sram_1kbyte_1rw1r_32x256_8 sram_inst (
// `ifdef USE_POWER_PINS
// .vccd1(vccd1),
// .vssd1(vssd1),
// `endif
// Port 0: RW
.clk0(clk),
.csb0(~req),
.web0(~we),
.wmask0(4'b1111), // 4-bit mask set to high to write all 32 bits
.addr0(addr),
.din0(data_in),
.dout0(sram_dout),

// Port 1: R (Tied off as it is unused in this design)
.clk1(1'b0),
.csb1(1'b1), // Active low, 1 disables the port
.addr1(8'b0),
.dout1()
);

always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_out <= 32'b0;
ready <= 1'b0;
end else begin
ready <= req;
if (req && !we) begin
data_out <= sram_dout;
end
end
end
endmodule

sram_macro.v

(* blackbox *)
module sky130_sram_1kbyte_1rw1r_32x256_8 (
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
// Port 0: RW
input clk0,
input csb0,
input web0,
input [3:0] wmask0,
input [7:0] addr0,
input [31:0] din0,
output [31:0] dout0,

// Port 1: R
input clk1,
input csb1,
input [7:0] addr1,
output [31:0] dout1
);
endmodule

==== Sources: macro/ ====

Note that there is another directory "macro/" where the files from sram PDK are placed.
This folder has the following files:

macro/sky130_sram_1kbyte_1rw1r_32x256_8.gds
macro/sky130_sram_1kbyte_1rw1r_32x256_8.lef
macro/sky130_sram_1kbyte_1rw1r_32x256_8.v
macro/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib

These have to be obtained from the PDK provider.
Here is more detailed documentation:
[https://armleo-openlane.readthedocs.io/en/merge-window-4/tutorials/openram.html Designing a chip with an OpenRAM (sky130)]

= Usecase: SRAM integration for IHP-Open-PDK =

This was tricky.
[https://www.dropbox.com/scl/fi/jm8g2u9ycb7xsnikelt60/readme_sram_ihp.pdf?rlkey=vjy3arvaovgtxju95jp01dhu4&raw=1 Here my notes (as a pdf file) describing the problems and fixes]

==== config.json ====
{
"DESIGN_NAME": "test_sram_ihp",
"PDK": "ihp-sg13g2",
"RUN_TAP_ENDCAP_INSERTION": false,
"PDN_MACRO_CONNECTIONS": [
"sram_inst VPWR VGND VDD! VSS!",
"sram_inst VPWR VGND VDDARRAY! VSS!"
],
"FP_PDN_CFG": "dir::src/pdn_cfg.tcl",
"RUN_MAGIC_STREAMOUT": false,
"RUN_MAGIC_WRITE_LEF": false,
"RUN_MAGIC_DRC": false,
"RUN_KLAYOUT_XOR": false,
"STD_CELL_LIBRARY": "sg13g2_stdcell",
"FP_SIZING": "absolute",
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"DIE_AREA": [0, 0, 800, 800],
"CORE_AREA": [10, 10, 790, 790],

"VERILOG_FILES": [
"dir::src/test_sram_ihp.v"
],
"VERILOG_FILES_BLACKBOX": [
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist_bb.v"
],

"EXTRA_LIBS": [
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist_typ_1p20V_25C.lib",
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist_slow_1p08V_125C.lib",
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist_fast_1p32V_m55C.lib"
],

"MACROS": {
"RM_IHPSG13_1P_256x32_c2_bm_bist": {
"gds": [
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist.gds"
],
"lef": [
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist.lef"
],
"instances": {
"sram_inst": {
"location": [200, 200],
"orientation": "N"
}
}
}
}
}

==== Sources: src/test_sram_ihp.v ====
module test_sram_ihp (
input wire clk,
input wire men, // Memory enable (active high)
input wire wen, // Write enable (active high)
input wire ren, // Read enable (active high)
input wire [31:0] bm, // 32-bit bit-mask for writing
input wire [7:0] addr, // 8 bits to address 256 words
input wire [31:0] din, // 32-bit data in
output wire [31:0] dout // 32-bit data out
);

// Instantiating the IHP 256x32 1-Port BIST macro
RM_IHPSG13_1P_256x32_c2_bm_bist sram_inst (
// Standard Operation Ports
.A_CLK (clk),
.A_MEN (men),
.A_WEN (wen),
.A_REN (ren),
.A_ADDR (addr),
.A_DIN (din),
.A_DOUT (dout),
.A_BM (bm),

// Mandatory Delay Pin
.A_DLY (1'b1), // Must be tied to 1

// BIST Ports - Tied off to 0 to disable BIST mode
.A_BIST_CLK (1'b0),
.A_BIST_EN (1'b0),
.A_BIST_MEN (1'b0),
.A_BIST_WEN (1'b0),
.A_BIST_REN (1'b0),
.A_BIST_ADDR (8'b0),
.A_BIST_DIN (32'b0),
.A_BIST_BM (32'b0)
);

endmodule

==== Sources: src/pdn_cfg.tcl ====
source $::env(SCRIPTS_DIR)/openroad/common/set_global_connections.tcl
set_global_connections

set secondary []
foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
if { $vdd != $::env(VDD_NET)} {
lappend secondary $vdd

set db_net [[ord::get_db_block] findNet $vdd]
if {$db_net == "NULL"} {
set net [odb::dbNet_create [ord::get_db_block] $vdd]
$net setSpecial
$net setSigType "POWER"
}
}

if { $gnd != $::env(GND_NET)} {
lappend secondary $gnd

set db_net [[ord::get_db_block] findNet $gnd]
if {$db_net == "NULL"} {
set net [odb::dbNet_create [ord::get_db_block] $gnd]
$net setSpecial
$net setSigType "GROUND"
}
}
}

set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
-secondary_power $secondary

if { $::env(FP_PDN_MULTILAYER) == 1 } {
define_pdn_grid \
-name stdcell_grid \
-starts_with POWER \
-voltage_domain CORE \
-pins "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"

add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_VERTICAL_LAYER) \
-width $::env(FP_PDN_VWIDTH) \
-pitch $::env(FP_PDN_VPITCH) \
-offset $::env(FP_PDN_VOFFSET) \
-spacing $::env(FP_PDN_VSPACING) \
-starts_with POWER -extend_to_core_ring

add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_HORIZONTAL_LAYER) \
-width $::env(FP_PDN_HWIDTH) \
-pitch $::env(FP_PDN_HPITCH) \
-offset $::env(FP_PDN_HOFFSET) \
-spacing $::env(FP_PDN_HSPACING) \
-starts_with POWER -extend_to_core_ring

add_pdn_connect \
-grid stdcell_grid \
-layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
} else {
define_pdn_grid \
-name stdcell_grid \
-starts_with POWER \
-voltage_domain CORE \
-pins $::env(FP_PDN_VERTICAL_LAYER)

add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_VERTICAL_LAYER) \
-width $::env(FP_PDN_VWIDTH) \
-pitch $::env(FP_PDN_VPITCH) \
-offset $::env(FP_PDN_VOFFSET) \
-spacing $::env(FP_PDN_VSPACING) \
-starts_with POWER -extend_to_core_ring
}

# Adds the standard cell rails if enabled.
if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_RAIL_LAYER) \
-width $::env(FP_PDN_RAIL_WIDTH) \
-followpins \
-starts_with POWER

add_pdn_connect \
-grid stdcell_grid \
-layers "$::env(FP_PDN_RAIL_LAYER) $::env(FP_PDN_VERTICAL_LAYER)"
}

# Adds the core ring if enabled.
if { $::env(FP_PDN_CORE_RING) == 1 } {
if { $::env(FP_PDN_MULTILAYER) == 1 } {
add_pdn_ring \
-grid stdcell_grid \
-layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)" \
-widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \
-spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
-core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
} else {
throw APPLICATION "FP_PDN_CORE_RING cannot be used when FP_PDN_MULTILAYER is set to false."
}
}

define_pdn_grid \
-macro \
-default \
-name macro \
-starts_with POWER \
-halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"

add_pdn_connect \
-grid macro \
-layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"

add_pdn_connect \
-grid macro \
-layers "Metal4 TopMetal1"

add_pdn_connect \
-grid macro \
-layers "Metal4 TopMetal2"

==== Sources: macro/ ====
The PDK sram files and some additional files go here.

RM_IHPSG13_1P_256x32_c2_bm_bist.gds
RM_IHPSG13_1P_256x32_c2_bm_bist.lef
RM_IHPSG13_1P_256x32_c2_bm_bist.txt
RM_IHPSG13_1P_256x32_c2_bm_bist.v
RM_IHPSG13_1P_256x32_c2_bm_bist_fast_1p32V_m55C.lib
RM_IHPSG13_1P_256x32_c2_bm_bist_slow_1p08V_125C.lib
RM_IHPSG13_1P_256x32_c2_bm_bist_typ_1p20V_25C.lib

This is a blackbox file, hiding the internals.
RM_IHPSG13_1P_256x32_c2_bm_bist_bb.v

It has the following content, matching the sram interface:

(* blackbox *)
module RM_IHPSG13_1P_256x32_c2_bm_bist (
input wire A_CLK,
input wire A_MEN,
input wire A_WEN,
input wire A_REN,
input wire [7:0] A_ADDR,
input wire [31:0] A_DIN,
input wire A_DLY,
output wire [31:0] A_DOUT,
input wire [31:0] A_BM,
input wire A_BIST_CLK,
input wire A_BIST_EN,
input wire A_BIST_MEN,
input wire A_BIST_WEN,
input wire A_BIST_REN,
input wire [7:0] A_BIST_ADDR,
input wire [31:0] A_BIST_DIN,
input wire [31:0] A_BIST_BM
);
endmodule

OpenLane 2

2026-07-03T20:25:37Z

Leo: /* Sources: src/pdn_cfg.tcl */

{{TocRight}}
OpenLane versions 1 and 2 is the VLSI design flow management framework.

However, it has been superseeded by [[LibreLane]] that is suggested for new designs.

= Setup Openline2 =
9https://openlane2.readthedocs.io/en/latest/getting_started/installation_overview.html The advised path]
is to setup NIX environment and then run openline2 from there, rather than using a dockerized version.

== Install Nix ==
Set up the Nix environment:
sudo apt-get install -y curl

curl --proto '=https' --tlsv1.2 -sSf -L https://install.determinate.systems/nix | sh -s -- install --no-confirm --extra-conf "
extra-substituters = https://openlane.cachix.org
extra-trusted-public-keys = openlane.cachix.org-1:qqdwh+QMNGmZAuyeQJTH9ErW57OWSvdtuwfBKdS254E=
"
Make sure to close all terminals after you’re done with this step.

=== If have Nix already ===

nix-env -f "<nixpkgs>" -iA cachix
sudo env PATH="$PATH" cachix use openlane
sudo pkill nix-daemon

== Install OpenLane 2 after Nix ==

git clone https://github.com/efabless/openlane2
nix-shell
openlane --smoke-test

== Other tools ==
There are many other tools you could setup separately, just know that openlane2 expects and is sensitive to the versions of the tools, and may not work if your tool is older or newer.

= My local setup =
This is how I use the Openlane2 tools after the setup.

One important note is that they generate MANY intermediate and log files in the "runs" directory under your project, every time you run openlane. This may take 6GB and more of the disk space for every run.

Usually my project is mapped to a cloud drive such as Dropbox, and spamming it with tons of files may create confusion when receiving an email later that someone has deleted 2000+ files from your account. Therefore I do the runs locally, possibly outside the project directory.
To achieve that, I run the following commands:

cd git.local/openlane2
nix-shell
openlane --smoke_test # Sanity test for the tools (optional)
cd your/project/

run_openlane_local.sh config.json # will save run logs under work.local/... (recommended)
or
opennlane config.json # will save the run logs in the project directory work/... (cloud?!)

= Setting up a new project =
A project is usually kept in one directory. It may contain:
* config.json file with the project options. Potentially you could have several configs, for different technologies, although probably berret to have a separate project for each.
* src/ directory with the Verilog or VHDL files
* runs/ directory with many intermediate and log files as populated by the openlane2 tool(s).
** The runs/ has a RUN<timestamp> folder for each openalne run. Each of those will have the following:
*** Folders from 01-... and up to 74-... or more with files according to the respective run steps
*** final/ directory with the final results, including the magic and klayout and gds files with the final layout, spice files, etc.
*** tmp - temporary directory.
*** flow, warning and error logs.

== The config.json file ==
Technically other formats such as yaml are also supported, but lets stick to json.
Here is an example of a simple config.json file for SKY PDK:
{
"DESIGN_NAME": "counter",
"VERILOG_FILES": ["src/counter.v"],
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"FP_CORE_UTIL": 40,
"RT_MAX_LAYER": "met4"
}

Here is another for IHP PDK:
{
"DESIGN_NAME": "counter",
"VERILOG_FILES": ["src/counter.v"],
"PDK": "sg13g2",
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"FP_CORE_UTIL": 40,
"RT_MAX_LAYER": "Metal4"
}
Here is a bit more with the die area:
{
"DESIGN_NAME": "adder_16bit",
"VERILOG_FILES": "dir::src/adder_16bit.v",
"CLOCK_TREE_SYNTH": false,
"CLOCK_PORT": null,
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 100 100",
"PL_TARGET_DENSITY": 0.65,
"VDD_NETS": ["vccd1"],
"GND_NETS": ["vssd1"],
"DIODE_INSERTION_STRATEGY": 4
}

= Usecase: Adder =
This is logic only, no registers

config.json
{
"DESIGN_NAME": "adder_16bit",
"VERILOG_FILES": "dir::src/adder_16bit.v",
"CLOCK_TREE_SYNTH": false,
"CLOCK_PORT": null,
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 100 100",
"PL_TARGET_DENSITY": 0.65,
"VDD_NETS": ["vccd1"],
"GND_NETS": ["vssd1"],
"DIODE_INSERTION_STRATEGY": 4
}

Verilog source (src/adder_16bit.v):
`default_nettype none
module adder_16bit (
input wire [15:0] a,
input wire [15:0] b,
input wire cin,
output wire [15:0] sum,
output wire cout
);
assign {cout, sum} = a + b + cin;
endmodule

= Usecase: Simple counter =
This design has a few registers

config.json
{
"DESIGN_NAME": "counter",
"VERILOG_FILES": ["src/counter.v"],
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"FP_CORE_UTIL": 40,
"RT_MAX_LAYER": "met4"
}

Verilog source (counter.v):
module counter (
input wire clk,
input wire reset,
output reg [15:0] count
);
always @(posedge clk or posedge reset) begin
if (reset)
count <= 16'b0;
else
count <= count + 1'b1;
end
endmodule

= Usecase: NeoRV32 MCU =

NeoRV32 is an open source MCU with many peripheral options written in VHDL.

* [https://github.com/stnolting/neorv32 GitHub repo] - Original VHDL version
* [https://github.com/stnolting/neorv32-verilog Repo for the verilog version] - A wrapper and converter script for Verilog

==== VHDL to Verilog ====
Openlane2 is using Yosis for synthesis, which natively supports Verilog.
Therefore we need to convert to a flat Verilog file. Therefore clone the second repository recursively:
git clone --recursive -j8 git@github.com:stnolting/neorv32-verilog.git
cd neorv32-verilog

Before the convertion go to the VHDL file and enable/disable the features you want.
Consider agressively disabling and downsizing everything to the minimum at least for the first runs so that the tools (e.g. yosys) can handle such a massive flat file.

cd git.local/neorv32-verilog/src/
edit* neorv32_verilog_wrapper.vhd

Go towards the end of the file and change true and false appropriately. Look for lines below the:
architecture neorv32_verilog_wrapper_rtl of neorv32_verilog_wrapper is
begin
...
generic map ( -- [note] add configuration options as required

Consider the following:
* "false" every "true" except as below
-- Internal Instruction memory (IMEM) --
IMEM_EN => true, -- implement processor-internal instruction memory
IMEM_SIZE => 16*16, -- size of processor-internal instruction memory in bytes
-- Internal Data memory (DMEM) --
DMEM_EN => true, -- implement processor-internal data memory
DMEM_SIZE => 8*32, -- size of processor-internal data memory in bytes
-- CPU Caches --
ICACHE_EN => true, -- implement instruction cache (i-cache)
ICACHE_NUM_BLOCKS => 4, -- i-cache: number of blocks (min 1), has to be a power of 2
DCACHE_EN => true, -- implement data cache (d-cache)
DCACHE_NUM_BLOCKS => 4, -- d-cache: number of blocks (min 1), has to be a power of 2
CACHE_BLOCK_SIZE => 64, -- i-cache/d-cache: block size in bytes (min 4), has to be a power of 2
...
IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
...
IO_PWM_NUM => 0, -- number of PWM channels to implement (0..32)

Install the ghdl for conversion unless already installed, and start the conversion process. Move the Verilog file to your project sourde directory when done:
sudo apt-get install ghdl
make check
make convert
mv src/neorv32_verilog_wrapper.v <your-project-dir>/src/

==== config.json ====
Some comments about the config file:
* Make sure to edit the vhdl and enable/disable only the components that you need. Or the tools may crash even with extra stack size on such a large flat file.
* "RUN_LINTER": false - othrvise here be errors on such a large flat file.
* You may need to specify a lot of size on the die:
"FP_SIZING": "absolute",
"DIE_AREA": [0, 0, 1000, 1000],
"CORE_AREA": [15, 15, 985, 985]
* Alternatively let the tools decide the size:
"FP_SIZING": "relative",
"FP_CORE_UTIL": 35,

The config.json file:
{
"DESIGN_NAME": "neorv32_verilog_wrapper",
"VERILOG_FILES": [
"dir::src/neorv32_verilog_wrapper.v"
],
"CLOCK_PORT": "clk_i",
"CLOCK_PERIOD": 25.0,
"PDK": "sky130A",
"STD_CELL_LIBRARY": "sky130_fd_sc_hd",
"FP_SIZING": "relative",
"FP_CORE_UTIL": 35,
"PL_TARGET_DENSITY_PCT": 40,
"SYNTH_STRATEGY": "AREA 0",
"VDD_NETS": [
"vccd1"
],
"GND_NETS": [
"vssd1"
],
"RUN_ANTENNA_REPAIR": true,
"RUN_HEURISTIC_DIODE_INSERTION": true,
"RUN_LINTER": false,

"_comment":
{
"FP_SIZING": "absolute",
"DIE_AREA": [0, 0, 1000, 1000],
"CORE_AREA": [15, 15, 985, 985]
}
}

==== Expected results ====
If all goes well, after an hour or so you may see the final remarks of the design in the terminal before it finishes.
A few important bits there:
#. DRC & LVS (Passed ✅)
#** DRC (Design Rule Check): The geometry of your standard cells, power straps, and routing wires strictly obeys the Sky130 foundry's physical manufacturing rules (minimum spacing, width, etc.).
#** LVS (Layout vs. Schematic): The final geometric layout perfectly matches your synthesized Verilog netlist. No unexpected shorts or open circuits were created during routing.
#. Antenna Violations (Failed 𐄂 - 8 Violations)
#* During plasma etching in fabrication, long metal wires act like antennas, collecting electrostatic charge that can blow out the thin gate oxides of connected transistors.
#* OpenLane attempted to fix these automatically (since we enabled RUN_ANTENNA_REPAIR), usually by jumping to higher metal layers or inserting "tie-down" diodes near the gates.
#* 8 violations simply mean a few nets are still too long relative to their connected gate area. In a real tape-out, you would manually inspect these in the GUI and force diode insertion or add routing blockages.
#. Max Slew & Max Cap Violations (Warnings)
#* These are electrical rule violations indicating that some signals are transitioning too slowly (slew) or driving too much load (capacitance).
#* Because we relied on OpenLane's generic fallback constraints rather than providing a custom .sdc (Synopsys Design Constraints) file, the timing-driven routing and buffer insertion heuristics were not strictly optimized for your specific 25ns clock period across all extreme temperature/voltage corners.
#* For a functional test run, these are completely safe to ignore.

==== OpenROAD ====
Now it is time to look at the generated layout.

# Force software-based OpenGL rendering
export LIBGL_ALWAYS_SOFTWARE=1

# Force Qt to use the X11 backend (bypassing native Wayland issues)
export QT_QPA_PLATFORM=xcb

openroad -gui

Then from the TCL commands console at the bottom of the OpenROAD GUI open your new design:
read_db runs/RUN_.../final/odb/neorv32_verilog_wrapper.odb

There in the tool you can proceed to the Display Control panel on the left to hide standard cells and inspect the routing layers.
* Under the Visibility tab, uncheck Instances (or specifically StdCells) to hide the internal logic gates.
* Expand the Layers menu. Here, you can toggle individual routing layers (met1, met2, met3, met4, met5) and vias to visually trace the physical connections across the die.

To jump directly to the physical wires that caused the antenna failures:
* In the top menu bar, navigate to Tools -> DRC Viewer.
* Click Load and navigate to the antenna report generated during your run.
You may need to look for the report file:
find runs/RUN_... -name "antenna.rpt"
This may find several reports. look for the latest one by OpenROAD:
runs/RUN_.../34-openroad-globalrouting/antenna.rpt
runs/RUN_.../37-odb-heuristicdiodeinsertion/3-openroad-globalrouting/antenna.rpt
runs/RUN_.../35-openroad-checkantennas/reports/antenna.rpt
runs/RUN_.../38-openroad-repairantennas/2-openroad-checkantennas/reports/antenna.rpt
runs/RUN_.../42-openroad-checkantennas-1/reports/antenna.rpt

Use the latest report by OpenROAD to open in the tool.
* The DRC Viewer will open a list of the violations, if any.
* Click on any violation in the list. The main camera will instantly pan, zoom, and highlight the exact wire segment and layer where the charge accumulation risk occurs.

= Usecase: SRAM integration for SKY (unfinished) =
Note, this design may still have unresolved issues (FIXME).
The magic tool has some issues with the sram implementation, therefore there are a few workarounds in the config file to depend mostly on klayout for the final steps.

==== config.json ====
{
"DESIGN_NAME": "top_module",
"VERILOG_FILES": [
"dir::src/top_module.v"
],
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,

"FP_SIZING": "absolute",
"DIE_AREA": [0.0, 0.0, 1000.0, 1000.0],

"VDD_NETS": ["vccd1"],
"GND_NETS": ["vssd1"],
"PDN_MACRO_CONNECTIONS": [
"sram_inst vccd1 vssd1 vccd1 vssd1"
],

"PRIMARY_GDSII_STREAMOUT_TOOL": "klayout",
"RUN_KLAYOUT_XOR": false,
"RUN_MAGIC_STREAMOUT": false,
"RUN_MAGIC_DRC": false,
"MAGIC_EXT_USE_GDS": false,
"MAGIC_INCLUDE_GDS_POINTERS": false,

"MACROS": {
"sky130_sram_1kbyte_1rw1r_32x256_8": {
"instances": {
"sram_inst": {
"location": [200.0, 200.0],
"orientation": "R0"
}
},
"vh": [
"dir::src/sram_macro.v"
],
"lef": [
"dir::macro/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
],
"gds": [
"dir::macro/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
],
"lib": {
"*": [
"dir::macro/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib"
]
}
}
}
}

==== Sources: src/ ====

top_module.v

module top_module (
// `ifdef USE_POWER_PINS
// inout vccd1,
// inout vssd1,
// `endif
input clk,
input rst_n,
input req,
input we,
input [7:0] addr,
input [31:0] data_in,
output reg [31:0] data_out,
output reg ready
);

wire [31:0] sram_dout;

// SRAM macro instantiation
sky130_sram_1kbyte_1rw1r_32x256_8 sram_inst (
// `ifdef USE_POWER_PINS
// .vccd1(vccd1),
// .vssd1(vssd1),
// `endif
// Port 0: RW
.clk0(clk),
.csb0(~req),
.web0(~we),
.wmask0(4'b1111), // 4-bit mask set to high to write all 32 bits
.addr0(addr),
.din0(data_in),
.dout0(sram_dout),

// Port 1: R (Tied off as it is unused in this design)
.clk1(1'b0),
.csb1(1'b1), // Active low, 1 disables the port
.addr1(8'b0),
.dout1()
);

always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_out <= 32'b0;
ready <= 1'b0;
end else begin
ready <= req;
if (req && !we) begin
data_out <= sram_dout;
end
end
end
endmodule

sram_macro.v

(* blackbox *)
module sky130_sram_1kbyte_1rw1r_32x256_8 (
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
// Port 0: RW
input clk0,
input csb0,
input web0,
input [3:0] wmask0,
input [7:0] addr0,
input [31:0] din0,
output [31:0] dout0,

// Port 1: R
input clk1,
input csb1,
input [7:0] addr1,
output [31:0] dout1
);
endmodule

==== Sources: macro/ ====

Note that there is another directory "macro/" where the files from sram PDK are placed.
This folder has the following files:

macro/sky130_sram_1kbyte_1rw1r_32x256_8.gds
macro/sky130_sram_1kbyte_1rw1r_32x256_8.lef
macro/sky130_sram_1kbyte_1rw1r_32x256_8.v
macro/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib

These have to be obtained from the PDK provider.
Here is more detailed documentation:
[https://armleo-openlane.readthedocs.io/en/merge-window-4/tutorials/openram.html Designing a chip with an OpenRAM (sky130)]

= Usecase: SRAM integration for IHP-Open-PDK =

This was tricky.
[https://www.dropbox.com/scl/fi/jm8g2u9ycb7xsnikelt60/readme_sram_ihp.pdf?rlkey=vjy3arvaovgtxju95jp01dhu4&raw=1 Here is a document describing the problems and fixes]

==== config.json ====
{
"DESIGN_NAME": "test_sram_ihp",
"PDK": "ihp-sg13g2",
"RUN_TAP_ENDCAP_INSERTION": false,
"PDN_MACRO_CONNECTIONS": [
"sram_inst VPWR VGND VDD! VSS!",
"sram_inst VPWR VGND VDDARRAY! VSS!"
],
"FP_PDN_CFG": "dir::src/pdn_cfg.tcl",
"RUN_MAGIC_STREAMOUT": false,
"RUN_MAGIC_WRITE_LEF": false,
"RUN_MAGIC_DRC": false,
"RUN_KLAYOUT_XOR": false,
"STD_CELL_LIBRARY": "sg13g2_stdcell",
"FP_SIZING": "absolute",
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"DIE_AREA": [0, 0, 800, 800],
"CORE_AREA": [10, 10, 790, 790],

"VERILOG_FILES": [
"dir::src/test_sram_ihp.v"
],
"VERILOG_FILES_BLACKBOX": [
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist_bb.v"
],

"EXTRA_LIBS": [
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist_typ_1p20V_25C.lib",
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist_slow_1p08V_125C.lib",
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist_fast_1p32V_m55C.lib"
],

"MACROS": {
"RM_IHPSG13_1P_256x32_c2_bm_bist": {
"gds": [
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist.gds"
],
"lef": [
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist.lef"
],
"instances": {
"sram_inst": {
"location": [200, 200],
"orientation": "N"
}
}
}
}
}

==== Sources: src/test_sram_ihp.v ====
module test_sram_ihp (
input wire clk,
input wire men, // Memory enable (active high)
input wire wen, // Write enable (active high)
input wire ren, // Read enable (active high)
input wire [31:0] bm, // 32-bit bit-mask for writing
input wire [7:0] addr, // 8 bits to address 256 words
input wire [31:0] din, // 32-bit data in
output wire [31:0] dout // 32-bit data out
);

// Instantiating the IHP 256x32 1-Port BIST macro
RM_IHPSG13_1P_256x32_c2_bm_bist sram_inst (
// Standard Operation Ports
.A_CLK (clk),
.A_MEN (men),
.A_WEN (wen),
.A_REN (ren),
.A_ADDR (addr),
.A_DIN (din),
.A_DOUT (dout),
.A_BM (bm),

// Mandatory Delay Pin
.A_DLY (1'b1), // Must be tied to 1

// BIST Ports - Tied off to 0 to disable BIST mode
.A_BIST_CLK (1'b0),
.A_BIST_EN (1'b0),
.A_BIST_MEN (1'b0),
.A_BIST_WEN (1'b0),
.A_BIST_REN (1'b0),
.A_BIST_ADDR (8'b0),
.A_BIST_DIN (32'b0),
.A_BIST_BM (32'b0)
);

endmodule

==== Sources: src/pdn_cfg.tcl ====
source $::env(SCRIPTS_DIR)/openroad/common/set_global_connections.tcl
set_global_connections

set secondary []
foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
if { $vdd != $::env(VDD_NET)} {
lappend secondary $vdd

set db_net [[ord::get_db_block] findNet $vdd]
if {$db_net == "NULL"} {
set net [odb::dbNet_create [ord::get_db_block] $vdd]
$net setSpecial
$net setSigType "POWER"
}
}

if { $gnd != $::env(GND_NET)} {
lappend secondary $gnd

set db_net [[ord::get_db_block] findNet $gnd]
if {$db_net == "NULL"} {
set net [odb::dbNet_create [ord::get_db_block] $gnd]
$net setSpecial
$net setSigType "GROUND"
}
}
}

set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
-secondary_power $secondary

if { $::env(FP_PDN_MULTILAYER) == 1 } {
define_pdn_grid \
-name stdcell_grid \
-starts_with POWER \
-voltage_domain CORE \
-pins "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"

add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_VERTICAL_LAYER) \
-width $::env(FP_PDN_VWIDTH) \
-pitch $::env(FP_PDN_VPITCH) \
-offset $::env(FP_PDN_VOFFSET) \
-spacing $::env(FP_PDN_VSPACING) \
-starts_with POWER -extend_to_core_ring

add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_HORIZONTAL_LAYER) \
-width $::env(FP_PDN_HWIDTH) \
-pitch $::env(FP_PDN_HPITCH) \
-offset $::env(FP_PDN_HOFFSET) \
-spacing $::env(FP_PDN_HSPACING) \
-starts_with POWER -extend_to_core_ring

add_pdn_connect \
-grid stdcell_grid \
-layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
} else {
define_pdn_grid \
-name stdcell_grid \
-starts_with POWER \
-voltage_domain CORE \
-pins $::env(FP_PDN_VERTICAL_LAYER)

add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_VERTICAL_LAYER) \
-width $::env(FP_PDN_VWIDTH) \
-pitch $::env(FP_PDN_VPITCH) \
-offset $::env(FP_PDN_VOFFSET) \
-spacing $::env(FP_PDN_VSPACING) \
-starts_with POWER -extend_to_core_ring
}

# Adds the standard cell rails if enabled.
if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_RAIL_LAYER) \
-width $::env(FP_PDN_RAIL_WIDTH) \
-followpins \
-starts_with POWER

add_pdn_connect \
-grid stdcell_grid \
-layers "$::env(FP_PDN_RAIL_LAYER) $::env(FP_PDN_VERTICAL_LAYER)"
}

# Adds the core ring if enabled.
if { $::env(FP_PDN_CORE_RING) == 1 } {
if { $::env(FP_PDN_MULTILAYER) == 1 } {
add_pdn_ring \
-grid stdcell_grid \
-layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)" \
-widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \
-spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
-core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
} else {
throw APPLICATION "FP_PDN_CORE_RING cannot be used when FP_PDN_MULTILAYER is set to false."
}
}

define_pdn_grid \
-macro \
-default \
-name macro \
-starts_with POWER \
-halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"

add_pdn_connect \
-grid macro \
-layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"

add_pdn_connect \
-grid macro \
-layers "Metal4 TopMetal1"

add_pdn_connect \
-grid macro \
-layers "Metal4 TopMetal2"

==== Sources: macro/ ====
The PDK sram files and some additional files go here.

RM_IHPSG13_1P_256x32_c2_bm_bist.gds
RM_IHPSG13_1P_256x32_c2_bm_bist.lef
RM_IHPSG13_1P_256x32_c2_bm_bist.txt
RM_IHPSG13_1P_256x32_c2_bm_bist.v
RM_IHPSG13_1P_256x32_c2_bm_bist_fast_1p32V_m55C.lib
RM_IHPSG13_1P_256x32_c2_bm_bist_slow_1p08V_125C.lib
RM_IHPSG13_1P_256x32_c2_bm_bist_typ_1p20V_25C.lib

This is a blackbox file, hiding the internals.
RM_IHPSG13_1P_256x32_c2_bm_bist_bb.v

It has the following content, matching the sram interface:

(* blackbox *)
module RM_IHPSG13_1P_256x32_c2_bm_bist (
input wire A_CLK,
input wire A_MEN,
input wire A_WEN,
input wire A_REN,
input wire [7:0] A_ADDR,
input wire [31:0] A_DIN,
input wire A_DLY,
output wire [31:0] A_DOUT,
input wire [31:0] A_BM,
input wire A_BIST_CLK,
input wire A_BIST_EN,
input wire A_BIST_MEN,
input wire A_BIST_WEN,
input wire A_BIST_REN,
input wire [7:0] A_BIST_ADDR,
input wire [31:0] A_BIST_DIN,
input wire [31:0] A_BIST_BM
);
endmodule

OpenLane 2

2026-07-03T20:25:01Z

Leo: /* Usecase: SRAM integration for IHP-Open-PDK */

{{TocRight}}
OpenLane versions 1 and 2 is the VLSI design flow management framework.

However, it has been superseeded by [[LibreLane]] that is suggested for new designs.

= Setup Openline2 =
9https://openlane2.readthedocs.io/en/latest/getting_started/installation_overview.html The advised path]
is to setup NIX environment and then run openline2 from there, rather than using a dockerized version.

== Install Nix ==
Set up the Nix environment:
sudo apt-get install -y curl

curl --proto '=https' --tlsv1.2 -sSf -L https://install.determinate.systems/nix | sh -s -- install --no-confirm --extra-conf "
extra-substituters = https://openlane.cachix.org
extra-trusted-public-keys = openlane.cachix.org-1:qqdwh+QMNGmZAuyeQJTH9ErW57OWSvdtuwfBKdS254E=
"
Make sure to close all terminals after you’re done with this step.

=== If have Nix already ===

nix-env -f "<nixpkgs>" -iA cachix
sudo env PATH="$PATH" cachix use openlane
sudo pkill nix-daemon

== Install OpenLane 2 after Nix ==

git clone https://github.com/efabless/openlane2
nix-shell
openlane --smoke-test

== Other tools ==
There are many other tools you could setup separately, just know that openlane2 expects and is sensitive to the versions of the tools, and may not work if your tool is older or newer.

= My local setup =
This is how I use the Openlane2 tools after the setup.

One important note is that they generate MANY intermediate and log files in the "runs" directory under your project, every time you run openlane. This may take 6GB and more of the disk space for every run.

Usually my project is mapped to a cloud drive such as Dropbox, and spamming it with tons of files may create confusion when receiving an email later that someone has deleted 2000+ files from your account. Therefore I do the runs locally, possibly outside the project directory.
To achieve that, I run the following commands:

cd git.local/openlane2
nix-shell
openlane --smoke_test # Sanity test for the tools (optional)
cd your/project/

run_openlane_local.sh config.json # will save run logs under work.local/... (recommended)
or
opennlane config.json # will save the run logs in the project directory work/... (cloud?!)

= Setting up a new project =
A project is usually kept in one directory. It may contain:
* config.json file with the project options. Potentially you could have several configs, for different technologies, although probably berret to have a separate project for each.
* src/ directory with the Verilog or VHDL files
* runs/ directory with many intermediate and log files as populated by the openlane2 tool(s).
** The runs/ has a RUN<timestamp> folder for each openalne run. Each of those will have the following:
*** Folders from 01-... and up to 74-... or more with files according to the respective run steps
*** final/ directory with the final results, including the magic and klayout and gds files with the final layout, spice files, etc.
*** tmp - temporary directory.
*** flow, warning and error logs.

== The config.json file ==
Technically other formats such as yaml are also supported, but lets stick to json.
Here is an example of a simple config.json file for SKY PDK:
{
"DESIGN_NAME": "counter",
"VERILOG_FILES": ["src/counter.v"],
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"FP_CORE_UTIL": 40,
"RT_MAX_LAYER": "met4"
}

Here is another for IHP PDK:
{
"DESIGN_NAME": "counter",
"VERILOG_FILES": ["src/counter.v"],
"PDK": "sg13g2",
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"FP_CORE_UTIL": 40,
"RT_MAX_LAYER": "Metal4"
}
Here is a bit more with the die area:
{
"DESIGN_NAME": "adder_16bit",
"VERILOG_FILES": "dir::src/adder_16bit.v",
"CLOCK_TREE_SYNTH": false,
"CLOCK_PORT": null,
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 100 100",
"PL_TARGET_DENSITY": 0.65,
"VDD_NETS": ["vccd1"],
"GND_NETS": ["vssd1"],
"DIODE_INSERTION_STRATEGY": 4
}

= Usecase: Adder =
This is logic only, no registers

config.json
{
"DESIGN_NAME": "adder_16bit",
"VERILOG_FILES": "dir::src/adder_16bit.v",
"CLOCK_TREE_SYNTH": false,
"CLOCK_PORT": null,
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 100 100",
"PL_TARGET_DENSITY": 0.65,
"VDD_NETS": ["vccd1"],
"GND_NETS": ["vssd1"],
"DIODE_INSERTION_STRATEGY": 4
}

Verilog source (src/adder_16bit.v):
`default_nettype none
module adder_16bit (
input wire [15:0] a,
input wire [15:0] b,
input wire cin,
output wire [15:0] sum,
output wire cout
);
assign {cout, sum} = a + b + cin;
endmodule

= Usecase: Simple counter =
This design has a few registers

config.json
{
"DESIGN_NAME": "counter",
"VERILOG_FILES": ["src/counter.v"],
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"FP_CORE_UTIL": 40,
"RT_MAX_LAYER": "met4"
}

Verilog source (counter.v):
module counter (
input wire clk,
input wire reset,
output reg [15:0] count
);
always @(posedge clk or posedge reset) begin
if (reset)
count <= 16'b0;
else
count <= count + 1'b1;
end
endmodule

= Usecase: NeoRV32 MCU =

NeoRV32 is an open source MCU with many peripheral options written in VHDL.

* [https://github.com/stnolting/neorv32 GitHub repo] - Original VHDL version
* [https://github.com/stnolting/neorv32-verilog Repo for the verilog version] - A wrapper and converter script for Verilog

==== VHDL to Verilog ====
Openlane2 is using Yosis for synthesis, which natively supports Verilog.
Therefore we need to convert to a flat Verilog file. Therefore clone the second repository recursively:
git clone --recursive -j8 git@github.com:stnolting/neorv32-verilog.git
cd neorv32-verilog

Before the convertion go to the VHDL file and enable/disable the features you want.
Consider agressively disabling and downsizing everything to the minimum at least for the first runs so that the tools (e.g. yosys) can handle such a massive flat file.

cd git.local/neorv32-verilog/src/
edit* neorv32_verilog_wrapper.vhd

Go towards the end of the file and change true and false appropriately. Look for lines below the:
architecture neorv32_verilog_wrapper_rtl of neorv32_verilog_wrapper is
begin
...
generic map ( -- [note] add configuration options as required

Consider the following:
* "false" every "true" except as below
-- Internal Instruction memory (IMEM) --
IMEM_EN => true, -- implement processor-internal instruction memory
IMEM_SIZE => 16*16, -- size of processor-internal instruction memory in bytes
-- Internal Data memory (DMEM) --
DMEM_EN => true, -- implement processor-internal data memory
DMEM_SIZE => 8*32, -- size of processor-internal data memory in bytes
-- CPU Caches --
ICACHE_EN => true, -- implement instruction cache (i-cache)
ICACHE_NUM_BLOCKS => 4, -- i-cache: number of blocks (min 1), has to be a power of 2
DCACHE_EN => true, -- implement data cache (d-cache)
DCACHE_NUM_BLOCKS => 4, -- d-cache: number of blocks (min 1), has to be a power of 2
CACHE_BLOCK_SIZE => 64, -- i-cache/d-cache: block size in bytes (min 4), has to be a power of 2
...
IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
...
IO_PWM_NUM => 0, -- number of PWM channels to implement (0..32)

Install the ghdl for conversion unless already installed, and start the conversion process. Move the Verilog file to your project sourde directory when done:
sudo apt-get install ghdl
make check
make convert
mv src/neorv32_verilog_wrapper.v <your-project-dir>/src/

==== config.json ====
Some comments about the config file:
* Make sure to edit the vhdl and enable/disable only the components that you need. Or the tools may crash even with extra stack size on such a large flat file.
* "RUN_LINTER": false - othrvise here be errors on such a large flat file.
* You may need to specify a lot of size on the die:
"FP_SIZING": "absolute",
"DIE_AREA": [0, 0, 1000, 1000],
"CORE_AREA": [15, 15, 985, 985]
* Alternatively let the tools decide the size:
"FP_SIZING": "relative",
"FP_CORE_UTIL": 35,

The config.json file:
{
"DESIGN_NAME": "neorv32_verilog_wrapper",
"VERILOG_FILES": [
"dir::src/neorv32_verilog_wrapper.v"
],
"CLOCK_PORT": "clk_i",
"CLOCK_PERIOD": 25.0,
"PDK": "sky130A",
"STD_CELL_LIBRARY": "sky130_fd_sc_hd",
"FP_SIZING": "relative",
"FP_CORE_UTIL": 35,
"PL_TARGET_DENSITY_PCT": 40,
"SYNTH_STRATEGY": "AREA 0",
"VDD_NETS": [
"vccd1"
],
"GND_NETS": [
"vssd1"
],
"RUN_ANTENNA_REPAIR": true,
"RUN_HEURISTIC_DIODE_INSERTION": true,
"RUN_LINTER": false,

"_comment":
{
"FP_SIZING": "absolute",
"DIE_AREA": [0, 0, 1000, 1000],
"CORE_AREA": [15, 15, 985, 985]
}
}

==== Expected results ====
If all goes well, after an hour or so you may see the final remarks of the design in the terminal before it finishes.
A few important bits there:
#. DRC & LVS (Passed ✅)
#** DRC (Design Rule Check): The geometry of your standard cells, power straps, and routing wires strictly obeys the Sky130 foundry's physical manufacturing rules (minimum spacing, width, etc.).
#** LVS (Layout vs. Schematic): The final geometric layout perfectly matches your synthesized Verilog netlist. No unexpected shorts or open circuits were created during routing.
#. Antenna Violations (Failed 𐄂 - 8 Violations)
#* During plasma etching in fabrication, long metal wires act like antennas, collecting electrostatic charge that can blow out the thin gate oxides of connected transistors.
#* OpenLane attempted to fix these automatically (since we enabled RUN_ANTENNA_REPAIR), usually by jumping to higher metal layers or inserting "tie-down" diodes near the gates.
#* 8 violations simply mean a few nets are still too long relative to their connected gate area. In a real tape-out, you would manually inspect these in the GUI and force diode insertion or add routing blockages.
#. Max Slew & Max Cap Violations (Warnings)
#* These are electrical rule violations indicating that some signals are transitioning too slowly (slew) or driving too much load (capacitance).
#* Because we relied on OpenLane's generic fallback constraints rather than providing a custom .sdc (Synopsys Design Constraints) file, the timing-driven routing and buffer insertion heuristics were not strictly optimized for your specific 25ns clock period across all extreme temperature/voltage corners.
#* For a functional test run, these are completely safe to ignore.

==== OpenROAD ====
Now it is time to look at the generated layout.

# Force software-based OpenGL rendering
export LIBGL_ALWAYS_SOFTWARE=1

# Force Qt to use the X11 backend (bypassing native Wayland issues)
export QT_QPA_PLATFORM=xcb

openroad -gui

Then from the TCL commands console at the bottom of the OpenROAD GUI open your new design:
read_db runs/RUN_.../final/odb/neorv32_verilog_wrapper.odb

There in the tool you can proceed to the Display Control panel on the left to hide standard cells and inspect the routing layers.
* Under the Visibility tab, uncheck Instances (or specifically StdCells) to hide the internal logic gates.
* Expand the Layers menu. Here, you can toggle individual routing layers (met1, met2, met3, met4, met5) and vias to visually trace the physical connections across the die.

To jump directly to the physical wires that caused the antenna failures:
* In the top menu bar, navigate to Tools -> DRC Viewer.
* Click Load and navigate to the antenna report generated during your run.
You may need to look for the report file:
find runs/RUN_... -name "antenna.rpt"
This may find several reports. look for the latest one by OpenROAD:
runs/RUN_.../34-openroad-globalrouting/antenna.rpt
runs/RUN_.../37-odb-heuristicdiodeinsertion/3-openroad-globalrouting/antenna.rpt
runs/RUN_.../35-openroad-checkantennas/reports/antenna.rpt
runs/RUN_.../38-openroad-repairantennas/2-openroad-checkantennas/reports/antenna.rpt
runs/RUN_.../42-openroad-checkantennas-1/reports/antenna.rpt

Use the latest report by OpenROAD to open in the tool.
* The DRC Viewer will open a list of the violations, if any.
* Click on any violation in the list. The main camera will instantly pan, zoom, and highlight the exact wire segment and layer where the charge accumulation risk occurs.

= Usecase: SRAM integration for SKY (unfinished) =
Note, this design may still have unresolved issues (FIXME).
The magic tool has some issues with the sram implementation, therefore there are a few workarounds in the config file to depend mostly on klayout for the final steps.

==== config.json ====
{
"DESIGN_NAME": "top_module",
"VERILOG_FILES": [
"dir::src/top_module.v"
],
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,

"FP_SIZING": "absolute",
"DIE_AREA": [0.0, 0.0, 1000.0, 1000.0],

"VDD_NETS": ["vccd1"],
"GND_NETS": ["vssd1"],
"PDN_MACRO_CONNECTIONS": [
"sram_inst vccd1 vssd1 vccd1 vssd1"
],

"PRIMARY_GDSII_STREAMOUT_TOOL": "klayout",
"RUN_KLAYOUT_XOR": false,
"RUN_MAGIC_STREAMOUT": false,
"RUN_MAGIC_DRC": false,
"MAGIC_EXT_USE_GDS": false,
"MAGIC_INCLUDE_GDS_POINTERS": false,

"MACROS": {
"sky130_sram_1kbyte_1rw1r_32x256_8": {
"instances": {
"sram_inst": {
"location": [200.0, 200.0],
"orientation": "R0"
}
},
"vh": [
"dir::src/sram_macro.v"
],
"lef": [
"dir::macro/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
],
"gds": [
"dir::macro/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
],
"lib": {
"*": [
"dir::macro/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib"
]
}
}
}
}

==== Sources: src/ ====

top_module.v

module top_module (
// `ifdef USE_POWER_PINS
// inout vccd1,
// inout vssd1,
// `endif
input clk,
input rst_n,
input req,
input we,
input [7:0] addr,
input [31:0] data_in,
output reg [31:0] data_out,
output reg ready
);

wire [31:0] sram_dout;

// SRAM macro instantiation
sky130_sram_1kbyte_1rw1r_32x256_8 sram_inst (
// `ifdef USE_POWER_PINS
// .vccd1(vccd1),
// .vssd1(vssd1),
// `endif
// Port 0: RW
.clk0(clk),
.csb0(~req),
.web0(~we),
.wmask0(4'b1111), // 4-bit mask set to high to write all 32 bits
.addr0(addr),
.din0(data_in),
.dout0(sram_dout),

// Port 1: R (Tied off as it is unused in this design)
.clk1(1'b0),
.csb1(1'b1), // Active low, 1 disables the port
.addr1(8'b0),
.dout1()
);

always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_out <= 32'b0;
ready <= 1'b0;
end else begin
ready <= req;
if (req && !we) begin
data_out <= sram_dout;
end
end
end
endmodule

sram_macro.v

(* blackbox *)
module sky130_sram_1kbyte_1rw1r_32x256_8 (
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
// Port 0: RW
input clk0,
input csb0,
input web0,
input [3:0] wmask0,
input [7:0] addr0,
input [31:0] din0,
output [31:0] dout0,

// Port 1: R
input clk1,
input csb1,
input [7:0] addr1,
output [31:0] dout1
);
endmodule

==== Sources: macro/ ====

Note that there is another directory "macro/" where the files from sram PDK are placed.
This folder has the following files:

macro/sky130_sram_1kbyte_1rw1r_32x256_8.gds
macro/sky130_sram_1kbyte_1rw1r_32x256_8.lef
macro/sky130_sram_1kbyte_1rw1r_32x256_8.v
macro/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib

These have to be obtained from the PDK provider.
Here is more detailed documentation:
[https://armleo-openlane.readthedocs.io/en/merge-window-4/tutorials/openram.html Designing a chip with an OpenRAM (sky130)]

= Usecase: SRAM integration for IHP-Open-PDK =

This was tricky.
[https://www.dropbox.com/scl/fi/jm8g2u9ycb7xsnikelt60/readme_sram_ihp.pdf?rlkey=vjy3arvaovgtxju95jp01dhu4&raw=1 Here is a document describing the problems and fixes]

==== config.json ====
{
"DESIGN_NAME": "test_sram_ihp",
"PDK": "ihp-sg13g2",
"RUN_TAP_ENDCAP_INSERTION": false,
"PDN_MACRO_CONNECTIONS": [
"sram_inst VPWR VGND VDD! VSS!",
"sram_inst VPWR VGND VDDARRAY! VSS!"
],
"FP_PDN_CFG": "dir::src/pdn_cfg.tcl",
"RUN_MAGIC_STREAMOUT": false,
"RUN_MAGIC_WRITE_LEF": false,
"RUN_MAGIC_DRC": false,
"RUN_KLAYOUT_XOR": false,
"STD_CELL_LIBRARY": "sg13g2_stdcell",
"FP_SIZING": "absolute",
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"DIE_AREA": [0, 0, 800, 800],
"CORE_AREA": [10, 10, 790, 790],

"VERILOG_FILES": [
"dir::src/test_sram_ihp.v"
],
"VERILOG_FILES_BLACKBOX": [
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist_bb.v"
],

"EXTRA_LIBS": [
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist_typ_1p20V_25C.lib",
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist_slow_1p08V_125C.lib",
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist_fast_1p32V_m55C.lib"
],

"MACROS": {
"RM_IHPSG13_1P_256x32_c2_bm_bist": {
"gds": [
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist.gds"
],
"lef": [
"dir::macros/RM_IHPSG13_1P_256x32_c2_bm_bist.lef"
],
"instances": {
"sram_inst": {
"location": [200, 200],
"orientation": "N"
}
}
}
}
}

==== Sources: src/test_sram_ihp.v ====
module test_sram_ihp (
input wire clk,
input wire men, // Memory enable (active high)
input wire wen, // Write enable (active high)
input wire ren, // Read enable (active high)
input wire [31:0] bm, // 32-bit bit-mask for writing
input wire [7:0] addr, // 8 bits to address 256 words
input wire [31:0] din, // 32-bit data in
output wire [31:0] dout // 32-bit data out
);

// Instantiating the IHP 256x32 1-Port BIST macro
RM_IHPSG13_1P_256x32_c2_bm_bist sram_inst (
// Standard Operation Ports
.A_CLK (clk),
.A_MEN (men),
.A_WEN (wen),
.A_REN (ren),
.A_ADDR (addr),
.A_DIN (din),
.A_DOUT (dout),
.A_BM (bm),

// Mandatory Delay Pin
.A_DLY (1'b1), // Must be tied to 1

// BIST Ports - Tied off to 0 to disable BIST mode
.A_BIST_CLK (1'b0),
.A_BIST_EN (1'b0),
.A_BIST_MEN (1'b0),
.A_BIST_WEN (1'b0),
.A_BIST_REN (1'b0),
.A_BIST_ADDR (8'b0),
.A_BIST_DIN (32'b0),
.A_BIST_BM (32'b0)
);

endmodule

==== Sources: src/pdn_cfg.tcl ====
source $::env(SCRIPTS_DIR)/openroad/common/set_global_connections.tcl
set_global_connections

set secondary []
foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
if { $vdd != $::env(VDD_NET)} {
lappend secondary $vdd

set db_net [[ord::get_db_block] findNet $vdd]
if {$db_net == "NULL"} {
set net [odb::dbNet_create [ord::get_db_block] $vdd]
$net setSpecial
$net setSigType "POWER"
}
}

if { $gnd != $::env(GND_NET)} {
lappend secondary $gnd

set db_net [[ord::get_db_block] findNet $gnd]
if {$db_net == "NULL"} {
set net [odb::dbNet_create [ord::get_db_block] $gnd]
$net setSpecial
$net setSigType "GROUND"
}
}
}

set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
-secondary_power $secondary

if { $::env(FP_PDN_MULTILAYER) == 1 } {
define_pdn_grid \
-name stdcell_grid \
-starts_with POWER \
-voltage_domain CORE \
-pins "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"

add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_VERTICAL_LAYER) \
-width $::env(FP_PDN_VWIDTH) \
-pitch $::env(FP_PDN_VPITCH) \
-offset $::env(FP_PDN_VOFFSET) \
-spacing $::env(FP_PDN_VSPACING) \
-starts_with POWER -extend_to_core_ring

add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_HORIZONTAL_LAYER) \
-width $::env(FP_PDN_HWIDTH) \
-pitch $::env(FP_PDN_HPITCH) \
-offset $::env(FP_PDN_HOFFSET) \
-spacing $::env(FP_PDN_HSPACING) \
-starts_with POWER -extend_to_core_ring

add_pdn_connect \
-grid stdcell_grid \
-layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
} else {
define_pdn_grid \
-name stdcell_grid \
-starts_with POWER \
-voltage_domain CORE \
-pins $::env(FP_PDN_VERTICAL_LAYER)

add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_VERTICAL_LAYER) \
-width $::env(FP_PDN_VWIDTH) \
-pitch $::env(FP_PDN_VPITCH) \
-offset $::env(FP_PDN_VOFFSET) \
-spacing $::env(FP_PDN_VSPACING) \
-starts_with POWER -extend_to_core_ring
}

# Adds the standard cell rails if enabled.
if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_RAIL_LAYER) \
-width $::env(FP_PDN_RAIL_WIDTH) \
-followpins \
-starts_with POWER

add_pdn_connect \
-grid stdcell_grid \
-layers "$::env(FP_PDN_RAIL_LAYER) $::env(FP_PDN_VERTICAL_LAYER)"
}

# Adds the core ring if enabled.
if { $::env(FP_PDN_CORE_RING) == 1 } {
if { $::env(FP_PDN_MULTILAYER) == 1 } {
add_pdn_ring \
-grid stdcell_grid \
-layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)" \
-widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \
-spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
-core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
} else {
throw APPLICATION "FP_PDN_CORE_RING cannot be used when FP_PDN_MULTILAYER is set to false."
}
}

define_pdn_grid \
-macro \
-default \
-name macro \
-starts_with POWER \
-halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"

add_pdn_connect \
-grid macro \
-layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"

add_pdn_connect \
-grid macro \
-layers "Metal4 TopMetal1"

add_pdn_connect \
-grid macro \
-layers "Metal4 TopMetal2"

==== Sources: macro/ ====
The PDK sram files and some additional files go here.

RM_IHPSG13_1P_256x32_c2_bm_bist.gds
RM_IHPSG13_1P_256x32_c2_bm_bist.lef
RM_IHPSG13_1P_256x32_c2_bm_bist.txt
RM_IHPSG13_1P_256x32_c2_bm_bist.v
RM_IHPSG13_1P_256x32_c2_bm_bist_fast_1p32V_m55C.lib
RM_IHPSG13_1P_256x32_c2_bm_bist_slow_1p08V_125C.lib
RM_IHPSG13_1P_256x32_c2_bm_bist_typ_1p20V_25C.lib

This is a blackbox file, hiding the internals.
RM_IHPSG13_1P_256x32_c2_bm_bist_bb.v

It has the following content, matching the sram interface:

(* blackbox *)
module RM_IHPSG13_1P_256x32_c2_bm_bist (
input wire A_CLK,
input wire A_MEN,
input wire A_WEN,
input wire A_REN,
input wire [7:0] A_ADDR,
input wire [31:0] A_DIN,
input wire A_DLY,
output wire [31:0] A_DOUT,
input wire [31:0] A_BM,
input wire A_BIST_CLK,
input wire A_BIST_EN,
input wire A_BIST_MEN,
input wire A_BIST_WEN,
input wire A_BIST_REN,
input wire [7:0] A_BIST_ADDR,
input wire [31:0] A_BIST_DIN,
input wire [31:0] A_BIST_BM
);
endmodule

OpenLane 2

2026-07-03T20:18:53Z

Leo: /* OpenROAD */

{{TocRight}}
OpenLane versions 1 and 2 is the VLSI design flow management framework.

However, it has been superseeded by [[LibreLane]] that is suggested for new designs.

= Setup Openline2 =
9https://openlane2.readthedocs.io/en/latest/getting_started/installation_overview.html The advised path]
is to setup NIX environment and then run openline2 from there, rather than using a dockerized version.

== Install Nix ==
Set up the Nix environment:
sudo apt-get install -y curl

curl --proto '=https' --tlsv1.2 -sSf -L https://install.determinate.systems/nix | sh -s -- install --no-confirm --extra-conf "
extra-substituters = https://openlane.cachix.org
extra-trusted-public-keys = openlane.cachix.org-1:qqdwh+QMNGmZAuyeQJTH9ErW57OWSvdtuwfBKdS254E=
"
Make sure to close all terminals after you’re done with this step.

=== If have Nix already ===

nix-env -f "<nixpkgs>" -iA cachix
sudo env PATH="$PATH" cachix use openlane
sudo pkill nix-daemon

== Install OpenLane 2 after Nix ==

git clone https://github.com/efabless/openlane2
nix-shell
openlane --smoke-test

== Other tools ==
There are many other tools you could setup separately, just know that openlane2 expects and is sensitive to the versions of the tools, and may not work if your tool is older or newer.

= My local setup =
This is how I use the Openlane2 tools after the setup.

One important note is that they generate MANY intermediate and log files in the "runs" directory under your project, every time you run openlane. This may take 6GB and more of the disk space for every run.

Usually my project is mapped to a cloud drive such as Dropbox, and spamming it with tons of files may create confusion when receiving an email later that someone has deleted 2000+ files from your account. Therefore I do the runs locally, possibly outside the project directory.
To achieve that, I run the following commands:

cd git.local/openlane2
nix-shell
openlane --smoke_test # Sanity test for the tools (optional)
cd your/project/

run_openlane_local.sh config.json # will save run logs under work.local/... (recommended)
or
opennlane config.json # will save the run logs in the project directory work/... (cloud?!)

= Setting up a new project =
A project is usually kept in one directory. It may contain:
* config.json file with the project options. Potentially you could have several configs, for different technologies, although probably berret to have a separate project for each.
* src/ directory with the Verilog or VHDL files
* runs/ directory with many intermediate and log files as populated by the openlane2 tool(s).
** The runs/ has a RUN<timestamp> folder for each openalne run. Each of those will have the following:
*** Folders from 01-... and up to 74-... or more with files according to the respective run steps
*** final/ directory with the final results, including the magic and klayout and gds files with the final layout, spice files, etc.
*** tmp - temporary directory.
*** flow, warning and error logs.

== The config.json file ==
Technically other formats such as yaml are also supported, but lets stick to json.
Here is an example of a simple config.json file for SKY PDK:
{
"DESIGN_NAME": "counter",
"VERILOG_FILES": ["src/counter.v"],
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"FP_CORE_UTIL": 40,
"RT_MAX_LAYER": "met4"
}

Here is another for IHP PDK:
{
"DESIGN_NAME": "counter",
"VERILOG_FILES": ["src/counter.v"],
"PDK": "sg13g2",
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"FP_CORE_UTIL": 40,
"RT_MAX_LAYER": "Metal4"
}
Here is a bit more with the die area:
{
"DESIGN_NAME": "adder_16bit",
"VERILOG_FILES": "dir::src/adder_16bit.v",
"CLOCK_TREE_SYNTH": false,
"CLOCK_PORT": null,
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 100 100",
"PL_TARGET_DENSITY": 0.65,
"VDD_NETS": ["vccd1"],
"GND_NETS": ["vssd1"],
"DIODE_INSERTION_STRATEGY": 4
}

= Usecase: Adder =
This is logic only, no registers

config.json
{
"DESIGN_NAME": "adder_16bit",
"VERILOG_FILES": "dir::src/adder_16bit.v",
"CLOCK_TREE_SYNTH": false,
"CLOCK_PORT": null,
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 100 100",
"PL_TARGET_DENSITY": 0.65,
"VDD_NETS": ["vccd1"],
"GND_NETS": ["vssd1"],
"DIODE_INSERTION_STRATEGY": 4
}

Verilog source (src/adder_16bit.v):
`default_nettype none
module adder_16bit (
input wire [15:0] a,
input wire [15:0] b,
input wire cin,
output wire [15:0] sum,
output wire cout
);
assign {cout, sum} = a + b + cin;
endmodule

= Usecase: Simple counter =
This design has a few registers

config.json
{
"DESIGN_NAME": "counter",
"VERILOG_FILES": ["src/counter.v"],
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"FP_CORE_UTIL": 40,
"RT_MAX_LAYER": "met4"
}

Verilog source (counter.v):
module counter (
input wire clk,
input wire reset,
output reg [15:0] count
);
always @(posedge clk or posedge reset) begin
if (reset)
count <= 16'b0;
else
count <= count + 1'b1;
end
endmodule

= Usecase: NeoRV32 MCU =

NeoRV32 is an open source MCU with many peripheral options written in VHDL.

* [https://github.com/stnolting/neorv32 GitHub repo] - Original VHDL version
* [https://github.com/stnolting/neorv32-verilog Repo for the verilog version] - A wrapper and converter script for Verilog

==== VHDL to Verilog ====
Openlane2 is using Yosis for synthesis, which natively supports Verilog.
Therefore we need to convert to a flat Verilog file. Therefore clone the second repository recursively:
git clone --recursive -j8 git@github.com:stnolting/neorv32-verilog.git
cd neorv32-verilog

Before the convertion go to the VHDL file and enable/disable the features you want.
Consider agressively disabling and downsizing everything to the minimum at least for the first runs so that the tools (e.g. yosys) can handle such a massive flat file.

cd git.local/neorv32-verilog/src/
edit* neorv32_verilog_wrapper.vhd

Go towards the end of the file and change true and false appropriately. Look for lines below the:
architecture neorv32_verilog_wrapper_rtl of neorv32_verilog_wrapper is
begin
...
generic map ( -- [note] add configuration options as required

Consider the following:
* "false" every "true" except as below
-- Internal Instruction memory (IMEM) --
IMEM_EN => true, -- implement processor-internal instruction memory
IMEM_SIZE => 16*16, -- size of processor-internal instruction memory in bytes
-- Internal Data memory (DMEM) --
DMEM_EN => true, -- implement processor-internal data memory
DMEM_SIZE => 8*32, -- size of processor-internal data memory in bytes
-- CPU Caches --
ICACHE_EN => true, -- implement instruction cache (i-cache)
ICACHE_NUM_BLOCKS => 4, -- i-cache: number of blocks (min 1), has to be a power of 2
DCACHE_EN => true, -- implement data cache (d-cache)
DCACHE_NUM_BLOCKS => 4, -- d-cache: number of blocks (min 1), has to be a power of 2
CACHE_BLOCK_SIZE => 64, -- i-cache/d-cache: block size in bytes (min 4), has to be a power of 2
...
IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
...
IO_PWM_NUM => 0, -- number of PWM channels to implement (0..32)

Install the ghdl for conversion unless already installed, and start the conversion process. Move the Verilog file to your project sourde directory when done:
sudo apt-get install ghdl
make check
make convert
mv src/neorv32_verilog_wrapper.v <your-project-dir>/src/

==== config.json ====
Some comments about the config file:
* Make sure to edit the vhdl and enable/disable only the components that you need. Or the tools may crash even with extra stack size on such a large flat file.
* "RUN_LINTER": false - othrvise here be errors on such a large flat file.
* You may need to specify a lot of size on the die:
"FP_SIZING": "absolute",
"DIE_AREA": [0, 0, 1000, 1000],
"CORE_AREA": [15, 15, 985, 985]
* Alternatively let the tools decide the size:
"FP_SIZING": "relative",
"FP_CORE_UTIL": 35,

The config.json file:
{
"DESIGN_NAME": "neorv32_verilog_wrapper",
"VERILOG_FILES": [
"dir::src/neorv32_verilog_wrapper.v"
],
"CLOCK_PORT": "clk_i",
"CLOCK_PERIOD": 25.0,
"PDK": "sky130A",
"STD_CELL_LIBRARY": "sky130_fd_sc_hd",
"FP_SIZING": "relative",
"FP_CORE_UTIL": 35,
"PL_TARGET_DENSITY_PCT": 40,
"SYNTH_STRATEGY": "AREA 0",
"VDD_NETS": [
"vccd1"
],
"GND_NETS": [
"vssd1"
],
"RUN_ANTENNA_REPAIR": true,
"RUN_HEURISTIC_DIODE_INSERTION": true,
"RUN_LINTER": false,

"_comment":
{
"FP_SIZING": "absolute",
"DIE_AREA": [0, 0, 1000, 1000],
"CORE_AREA": [15, 15, 985, 985]
}
}

==== Expected results ====
If all goes well, after an hour or so you may see the final remarks of the design in the terminal before it finishes.
A few important bits there:
#. DRC & LVS (Passed ✅)
#** DRC (Design Rule Check): The geometry of your standard cells, power straps, and routing wires strictly obeys the Sky130 foundry's physical manufacturing rules (minimum spacing, width, etc.).
#** LVS (Layout vs. Schematic): The final geometric layout perfectly matches your synthesized Verilog netlist. No unexpected shorts or open circuits were created during routing.
#. Antenna Violations (Failed 𐄂 - 8 Violations)
#* During plasma etching in fabrication, long metal wires act like antennas, collecting electrostatic charge that can blow out the thin gate oxides of connected transistors.
#* OpenLane attempted to fix these automatically (since we enabled RUN_ANTENNA_REPAIR), usually by jumping to higher metal layers or inserting "tie-down" diodes near the gates.
#* 8 violations simply mean a few nets are still too long relative to their connected gate area. In a real tape-out, you would manually inspect these in the GUI and force diode insertion or add routing blockages.
#. Max Slew & Max Cap Violations (Warnings)
#* These are electrical rule violations indicating that some signals are transitioning too slowly (slew) or driving too much load (capacitance).
#* Because we relied on OpenLane's generic fallback constraints rather than providing a custom .sdc (Synopsys Design Constraints) file, the timing-driven routing and buffer insertion heuristics were not strictly optimized for your specific 25ns clock period across all extreme temperature/voltage corners.
#* For a functional test run, these are completely safe to ignore.

==== OpenROAD ====
Now it is time to look at the generated layout.

# Force software-based OpenGL rendering
export LIBGL_ALWAYS_SOFTWARE=1

# Force Qt to use the X11 backend (bypassing native Wayland issues)
export QT_QPA_PLATFORM=xcb

openroad -gui

Then from the TCL commands console at the bottom of the OpenROAD GUI open your new design:
read_db runs/RUN_.../final/odb/neorv32_verilog_wrapper.odb

There in the tool you can proceed to the Display Control panel on the left to hide standard cells and inspect the routing layers.
* Under the Visibility tab, uncheck Instances (or specifically StdCells) to hide the internal logic gates.
* Expand the Layers menu. Here, you can toggle individual routing layers (met1, met2, met3, met4, met5) and vias to visually trace the physical connections across the die.

To jump directly to the physical wires that caused the antenna failures:
* In the top menu bar, navigate to Tools -> DRC Viewer.
* Click Load and navigate to the antenna report generated during your run.
You may need to look for the report file:
find runs/RUN_... -name "antenna.rpt"
This may find several reports. look for the latest one by OpenROAD:
runs/RUN_.../34-openroad-globalrouting/antenna.rpt
runs/RUN_.../37-odb-heuristicdiodeinsertion/3-openroad-globalrouting/antenna.rpt
runs/RUN_.../35-openroad-checkantennas/reports/antenna.rpt
runs/RUN_.../38-openroad-repairantennas/2-openroad-checkantennas/reports/antenna.rpt
runs/RUN_.../42-openroad-checkantennas-1/reports/antenna.rpt

Use the latest report by OpenROAD to open in the tool.
* The DRC Viewer will open a list of the violations, if any.
* Click on any violation in the list. The main camera will instantly pan, zoom, and highlight the exact wire segment and layer where the charge accumulation risk occurs.

= Usecase: SRAM integration for SKY (unfinished) =
Note, this design may still have unresolved issues (FIXME).
The magic tool has some issues with the sram implementation, therefore there are a few workarounds in the config file to depend mostly on klayout for the final steps.

==== config.json ====
{
"DESIGN_NAME": "top_module",
"VERILOG_FILES": [
"dir::src/top_module.v"
],
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,

"FP_SIZING": "absolute",
"DIE_AREA": [0.0, 0.0, 1000.0, 1000.0],

"VDD_NETS": ["vccd1"],
"GND_NETS": ["vssd1"],
"PDN_MACRO_CONNECTIONS": [
"sram_inst vccd1 vssd1 vccd1 vssd1"
],

"PRIMARY_GDSII_STREAMOUT_TOOL": "klayout",
"RUN_KLAYOUT_XOR": false,
"RUN_MAGIC_STREAMOUT": false,
"RUN_MAGIC_DRC": false,
"MAGIC_EXT_USE_GDS": false,
"MAGIC_INCLUDE_GDS_POINTERS": false,

"MACROS": {
"sky130_sram_1kbyte_1rw1r_32x256_8": {
"instances": {
"sram_inst": {
"location": [200.0, 200.0],
"orientation": "R0"
}
},
"vh": [
"dir::src/sram_macro.v"
],
"lef": [
"dir::macro/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
],
"gds": [
"dir::macro/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
],
"lib": {
"*": [
"dir::macro/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib"
]
}
}
}
}

==== Sources: src/ ====

top_module.v

module top_module (
// `ifdef USE_POWER_PINS
// inout vccd1,
// inout vssd1,
// `endif
input clk,
input rst_n,
input req,
input we,
input [7:0] addr,
input [31:0] data_in,
output reg [31:0] data_out,
output reg ready
);

wire [31:0] sram_dout;

// SRAM macro instantiation
sky130_sram_1kbyte_1rw1r_32x256_8 sram_inst (
// `ifdef USE_POWER_PINS
// .vccd1(vccd1),
// .vssd1(vssd1),
// `endif
// Port 0: RW
.clk0(clk),
.csb0(~req),
.web0(~we),
.wmask0(4'b1111), // 4-bit mask set to high to write all 32 bits
.addr0(addr),
.din0(data_in),
.dout0(sram_dout),

// Port 1: R (Tied off as it is unused in this design)
.clk1(1'b0),
.csb1(1'b1), // Active low, 1 disables the port
.addr1(8'b0),
.dout1()
);

always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_out <= 32'b0;
ready <= 1'b0;
end else begin
ready <= req;
if (req && !we) begin
data_out <= sram_dout;
end
end
end
endmodule

sram_macro.v

(* blackbox *)
module sky130_sram_1kbyte_1rw1r_32x256_8 (
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
// Port 0: RW
input clk0,
input csb0,
input web0,
input [3:0] wmask0,
input [7:0] addr0,
input [31:0] din0,
output [31:0] dout0,

// Port 1: R
input clk1,
input csb1,
input [7:0] addr1,
output [31:0] dout1
);
endmodule

==== Sources: macro/ ====

Note that there is another directory "macro/" where the files from sram PDK are placed.
This folder has the following files:

macro/sky130_sram_1kbyte_1rw1r_32x256_8.gds
macro/sky130_sram_1kbyte_1rw1r_32x256_8.lef
macro/sky130_sram_1kbyte_1rw1r_32x256_8.v
macro/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib

These have to be obtained from the PDK provider.
Here is more detailed documentation:
[https://armleo-openlane.readthedocs.io/en/merge-window-4/tutorials/openram.html Designing a chip with an OpenRAM (sky130)]

= Usecase: SRAM integration for IHP-Open-PDK =

This was tricky.
[https://www.dropbox.com/scl/fi/jm8g2u9ycb7xsnikelt60/readme_sram_ihp.pdf?rlkey=vjy3arvaovgtxju95jp01dhu4&raw=1 Here is a document describing the problems and fixes]

==== Sources: macro/ ====
The PDK sram files and some additional files go here.

RM_IHPSG13_1P_256x32_c2_bm_bist.gds
RM_IHPSG13_1P_256x32_c2_bm_bist.lef
RM_IHPSG13_1P_256x32_c2_bm_bist.txt
RM_IHPSG13_1P_256x32_c2_bm_bist.v
RM_IHPSG13_1P_256x32_c2_bm_bist_fast_1p32V_m55C.lib
RM_IHPSG13_1P_256x32_c2_bm_bist_slow_1p08V_125C.lib
RM_IHPSG13_1P_256x32_c2_bm_bist_typ_1p20V_25C.lib

This is a blackbox file, hiding the internals.
RM_IHPSG13_1P_256x32_c2_bm_bist_bb.v

It has the following content, matching the sram interface:

(* blackbox *)
module RM_IHPSG13_1P_256x32_c2_bm_bist (
input wire A_CLK,
input wire A_MEN,
input wire A_WEN,
input wire A_REN,
input wire [7:0] A_ADDR,
input wire [31:0] A_DIN,
input wire A_DLY,
output wire [31:0] A_DOUT,
input wire [31:0] A_BM,
input wire A_BIST_CLK,
input wire A_BIST_EN,
input wire A_BIST_MEN,
input wire A_BIST_WEN,
input wire A_BIST_REN,
input wire [7:0] A_BIST_ADDR,
input wire [31:0] A_BIST_DIN,
input wire [31:0] A_BIST_BM
);
endmodule

2026-05-07T11:13:53Z

Leo: /* Instalē atbalsta bibliotēkas */

= Īsumā =
''(Šis ir izmēģināts ar Ubuntu 22.04)''

==== Lejuplādē ====
** ISE instalāciju iespējams lejuplādēt no [https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive-ise.html Xilinx arhīva web portāla], kurā nepieciešams šim nolūkam izveidot kontu.

==== Instalē atbalsta bibliotēkas ====

sudo apt install libncurses5

Jaunākai sistēmai (Ubuntu 26+), kur libncurses5 nomainījusi libncurses6, var mēģināt:
sudo ln -s /usr/lib/x86_64-linux-gnu/libncurses.so.6 /usr/lib/x86_64-linux-gnu/libncurses.so.5

==== Instalē ISE ====
No atarhivētās direktorijas
sudo chmod a+x xsetup
sudo ./xsetup

Seko instalācijai
* Piekrīt licensēm
* Uncheck "Install cable drivers"
* Izvēlas WebPack (vai System edition pilnai versijai)
* Instalācijas vieta: /opt/Xilinx
* Licensi, ko saņem no Xilinx, tai skaitā studentu brīvo licensi, vai pielikt arī vēlāk.

Izmēģina
Uztaisam skriptu ise.sh palaišanai:

cd /opt/Xilinx/14.7/ISE_DS
. ./settings64.sh

Pieliek taciņas
export PATH=$PATH:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64
ise

==== Instalē Digilent Adept ====
Priekš ANVYL un jaunākiem attīstītājrīkiem
* Runtime
* Utilities

= Papildus info =
Xilinx ISE Webpack versija 14.7 (Windows 7, nevis Windows 10) ir pēdējā versija, kas vēl atbalsta Spartan 3E FPGA.

* [[ISE WebPACK 14.7 USB driver]] instalācija (vecākiem Spartan 3E rīkiem)
* Jaunākiem (ANVYL) rīkem - [https://digilent.com/reference/software/adept/start Digilent Adept] jāinstallē Utilities un Runtime
Papildus:
* [https://www.xilinx.com/support/answers/59128.html Digilent driver installation] (no Xilinx portāla)
* [http://dreamrunner.org/blog/2012/09/12/install-xilinx-ise-on-the-ubuntu/ Install Xilinx ISE on Ubuntu] (learn&think)
* [https://www.george-smart.co.uk/fpga/xilinx_jtag_linux/ Install Linux ISE] (George Smart)

* [https://www.programmersought.com/article/24731802295/ ISE instalācija uz Ubuntu 18]