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'''Shortcuts:'''
[[#Calendar | Calendar]] |
[[#Assignments | Assignments]] |
[[#Resources | Resources]] |
[[#{{CURRENTDAY2}}.{{CURRENTMONTH}}.{{CURRENTYEAR}} | Today <small>(if there is a class)</small>]]
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'''Course: Assembly Programming'''

=Calendar=
{| border=1 cellspacing=0 cellpadding=4 style = 'border-color: #ddd;'
|-
! Date
! Topic, content
! Deliverables

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====19.09.2023====
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{| width='100%' style='background-color:#ddd;'
|<big>'''Introduction'''</big>
|}
Microprocessors and microcontrollers. Applications. Architectures. Coourse outline.

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====19.09.2023====
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{| width='100%' style='background-color:#ddd;'
|<big>'''Hexadecimal arithmetic'''</big>
|}
Representation of non-negative numbers in hardware, registers and memory. Decimal, binary, octal, and hexadecimal systems. Converting between the systems.

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====26.09.2023====
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{| width='100%' style='background-color:#ddd;'
|<big>'''Two's complement'''</big>
|}
Representing negative numbers in hardware. Register size, and why it is important. Methods for encoding negative numbers: packed, signed, bias, one's complement and two's complement. Converting between the value and two's complement in binary and hexadecimal systems.

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'''Quiz 1'''

Decimal, binary, octal and hexadecimal systems.

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====03.10.2023====
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{| width='100%' style='background-color:#ddd;'
|<big>'''Processor architecture'''</big>
|}
Architecture of a processor. Registers, register file, ALU, datapath. CISC vs. RISC architectures. x86 architecture as CISC representative. ARM architecture as RISC. Instruction encoding.

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'''Quiz 2''' (rescheduled to next week)
Two's complement.

Lab:

Developing and testing a simple Assembly program. Using cross-compilation tools. Introduction to the Make system.

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====10.10.2023====
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{| width='100%' style='background-color:#ddd;'
|<big>'''Computing environment'''</big>
|}
Environment and tools for compiling and debugging Assembly programs. Compiler, preprocessor, assembly, linker, loader, debugger. Cross-compilation and toolchains. Emulators and virtual machines.

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'''Quiz 2'''

Two's complement.

Announced: '''HW1''' - Arithmetic progression
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====17.10.2023====
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{| width='100%' style='background-color:#ddd;'
|<big>'''ARM Assembly and arithmetic'''</big>
|}
Introduction to ARM Assembly language and programming. Instruction types. Arithmetic instructions. MOV, ADD, SUB. MVN, ADC, SBC, RSB, RSC. Barrel Shifter.

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Practicing tracing the code (on "paper")

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====24.10.2023====
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{| width='100%' style='background-color:#ddd;'
|<big>'''Flow control and tests'''</big>
|}
Flow control in Assembly. Branch instructions. B, BL, BX, BLX. Working directly with PC register. CPSR flags. Condition field. Bit operations. AND, ORR, EOR, BIC, shift and rotation. CMP, CMN, TST, TEQ. Fast flags and the S postfix.

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Code comprehension practice.

* Announced: '''HW2''' - Matrix multiplication

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====31.10.2023====
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{| width='100%' style='background-color:#ddd;'
|<big>'''Memory instructions'''</big>
|}
Reading and writing data to memory. Memory access instructions. STR, LDR, STRB, STRH, LDRB, LDRH, LDRSB, LDRSH. Addressing modes: offset, pre-indexed and post-indexed. Using barrel shifter with addressing. Data alignment in memory.

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* '''Quiz 3''' - Code comprehension (moved)

* '''Due''' '''HW1''' - Arithmetic progression

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====07.11.2023====
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{| width='100%' style='background-color:#ddd;'
|<big>'''Calling subroutines and interfacing with C'''</big>
|}
Variable types in C: static, automatic and dynamic. Calling subroutines and parameter passing conventions. Parameters and return value. Stack and registers. Saving the registers, the context. Loading and storing multiple registers: LDM, STM. Interfacing between Assembly and C.

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====14.11.2023====
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{| width='100%' style='background-color:#ddd;'
|<big>'''Symbols'''</big>
|}
Symbol encoding in hardware and software. Code tables. ASCII. EBCDIC. ISO code tables. Foreign letter symbols. UTF-8, UTF-16. Strings in C and memory. Converting values to symbols and strings.

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* '''Quiz 3''' - Code comprehension
* '''Due''' '''HW2''' - Matrix multiplication

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====21.11.2023====
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{| width='100%' style='background-color:#ddd;'
|<big>'''Midterm'''</big>
|}
Data representation in memory.
Assembly code comprehension.
Two programming tasks.

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* Assignment '''Proj''' - Project choice

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====28.11.2023====
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{| width='100%' style='background-color:#ddd;'
|<big>'''Expressions and Macro commands'''</big>
|}
Expressions in Assembly. Operators in expressions. Constants. Assigning values to symbols. Directives: .set, .equiv, .eqv. Conditional compilation. Directives .if, .ifdef, .endif., ifb, .ifc, .ifeqs. More conditionals .ifeq, .ifge, .ifne and others. Macro commands: .macro, .endm., .rept. Recursive macros. Local macros. Macros across sections.

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* '''Due''' '''M1P1''' - Midterm 1 programming task 1, tested
* '''Due''' '''M1P2''' - Midterm 1 programming task 2, tested


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====05.12.2023====
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{| width='100%' style='background-color:#ddd;'
|<big>'''Inline Assembly'''</big>
|}
Including Assembly in C code. Inline code and Assembly code operands. Tasks for the compiler, linker and loader. Dynamic loaders and libraries.

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Due: Choice: Written exam vs. programming project (in eStudijas)
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====12.12.2023====
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{| width='100%' style='background-color:#ddd;'
|<big>'''Optimizations'''</big>
|}
Execution time for instructions. Case study for code optimization. Leveraging the documentation and specification of instructions. Reordering the code. Unrolling loops. Taking advantage of branch prediction. Cache memory and the code performance.

Documentation: [http://download.intel.com/design/intelxscale/27347302.pdf Intel XScale R Core Developer’s Manual].

The section and focus:
* A.2.1.2 — Processor execution pipe diagram. Instruction and data flow description.
* 10.4 — Instruction execution time. For example, multiplication vs. addition.
* 5 — Branch prediction mechanism
* 4 and 6 — Cache memory. Instruction cache and Data cache.
* A.3–A.5 — Optimizations as suggested by Intel.

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====12.12.2023====
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{| width='100%' style='background-color:#ddd;'
|<big>'''Systems on chip (SoC)'''</big>
|}

* Datasheets
* Memory map
* Communications protocols (RS232, USB, SPI, I2C, 1-wire, CAN)
* Peripherals
* Watchdog timer
* Bootstraping

Case study:
* Atmega328P MCU ([https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-7810-Automotive-Microcontrollers-ATmega328P_Datasheet.pdf datasheet])
* [https://www.elprocus.com/avr-atmega8-microcontroller-architecture-applications/ Atmega8 architecture description]

'''Review of the course topics'''

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====02.01.2024====
12:30
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{| width='100%' style='background-color:#ddd;'
|<big>'''Exam'''</big>
|}
Data representation in memory.
Assembly code comprehension.
Multiple choice questions and a programming task.

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* '''Due''' by the end of the day: '''ExP1''' - Exam programming task, tested
|}

=Assignments=
* Homeworks and other assignments are available from e-Studijas

{{MCU_resources}}

LU-MOP-en23 - Revision history

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