VLSI - Revision history

Leo at 19:57, 3 July 2026

2026-07-03T19:57:07Z

← Older revision		Revision as of 19:57, 3 July 2026
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	* OpenRoad - Automates floorplanning, placement, routing and timing.		* OpenRoad - Automates floorplanning, placement, routing and timing.
	* OpenLane - (obsolete) Automated design flow, from verilog to GDSII, uses the tools above.		* OpenLane - (obsolete) Automated design flow, from verilog to GDSII, uses the tools above.
	* LibreLane - ~~superceeds~~ the OpenLane.		* LibreLane - superseeds the OpenLane.

	== Open Technology PDKs ==		== Open Technology PDKs ==

Leo at 19:54, 3 July 2026

2026-07-03T19:54:09Z

Show changes

Leo: /* Open Tools */

2026-07-03T19:49:49Z

Open Tools

← Older revision		Revision as of 19:49, 3 July 2026
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	* KLayout - viewer and editor of GDSII files		* KLayout - viewer and editor of GDSII files
	* OpenRoad - Automates floorplanning, placement, routing and timing.		* OpenRoad - Automates floorplanning, placement, routing and timing.
	* OpenLane - Automated design flow, from verilog to GDSII, uses the tools above.		* OpenLane - (obsolete) Automated design flow, from verilog to GDSII, uses the tools above.
			* LibreLane - superceeds the OpenLane.

	== Open Technology PDKs ==		== Open Technology PDKs ==

Leo: /* OpenRoad */

2026-06-19T17:44:53Z

OpenRoad

← Older revision		Revision as of 17:44, 19 June 2026
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	#* For a functional test run, these are completely safe to ignore.		#* For a functional test run, these are completely safe to ignore.

	==== ~~OpenRoad~~ ====		==== OpenROAD ====
	Now it is time to look at the generated layout.		Now it is time to look at the generated layout.

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	To jump directly to the physical wires that caused the antenna failures:		To jump directly to the physical wires that caused the antenna failures:
	* In the top menu bar, navigate to Tools -> DRC Viewer.		* In the top menu bar, navigate to Tools -> DRC Viewer.
	* Click Load and navigate to the antenna report generated during your run. ~~This is typically located at:~~		* Click Load and navigate to the antenna report generated during your run.
			You may need to look for the report file:
	runs/RUN_.../reports/routing/antenna.rpt (or an equivalent .json or .lyrdb file in the signoff/routing reports directory).
			find runs/RUN_... -name "antenna.rpt"
			This may find several reports. look for the latest one by OpenROAD:
			runs/RUN_.../34-openroad-globalrouting/antenna.rpt
			runs/RUN_.../37-odb-heuristicdiodeinsertion/3-openroad-globalrouting/antenna.rpt
			runs/RUN_.../35-openroad-checkantennas/reports/antenna.rpt
			runs/RUN_.../38-openroad-repairantennas/2-openroad-checkantennas/reports/antenna.rpt
			runs/RUN_.../42-openroad-checkantennas-1/reports/antenna.rpt

			Use the latest report by OpenROAD to open in the tool.
	* The DRC Viewer will open a list of the violations, if any.		* The DRC Viewer will open a list of the violations, if any.
	* Click on any violation in the list. The main camera will instantly pan, zoom, and highlight the exact wire segment and layer where the charge accumulation risk occurs.		* Click on any violation in the list. The main camera will instantly pan, zoom, and highlight the exact wire segment and layer where the charge accumulation risk occurs.

Leo: /* OpenRoad */

2026-06-19T17:35:35Z

OpenRoad

← Older revision		Revision as of 17:35, 19 June 2026
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	* In the top menu bar, navigate to Tools -> DRC Viewer.		* In the top menu bar, navigate to Tools -> DRC Viewer.
	* Click Load and navigate to the antenna report generated during your run. This is typically located at:		* Click Load and navigate to the antenna report generated during your run. This is typically located at:
	runs/RUN_.../reports/routing/antenna.rpt (or an equivalent .json or .lyrdb file in the signoff/routing reports directory).		runs/RUN_.../reports/routing/antenna.rpt (or an equivalent .json or .lyrdb file in the signoff/routing reports directory).
	* The DRC Viewer will open a list of the violations, if any.		* The DRC Viewer will open a list of the violations, if any.
	* Click on any violation in the list. The main camera will instantly pan, zoom, and highlight the exact wire segment and layer where the charge accumulation risk occurs.		* Click on any violation in the list. The main camera will instantly pan, zoom, and highlight the exact wire segment and layer where the charge accumulation risk occurs.

Leo: /* Expected results */

2026-06-19T17:34:57Z

Expected results

← Older revision		Revision as of 17:34, 19 June 2026
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	#* For a functional test run, these are completely safe to ignore.		#* For a functional test run, these are completely safe to ignore.

			==== OpenRoad ====
	Now it is time to look at the generated layout.		Now it is time to look at the generated layout.

			# Force software-based OpenGL rendering
			export LIBGL_ALWAYS_SOFTWARE=1

			# Force Qt to use the X11 backend (bypassing native Wayland issues)
			export QT_QPA_PLATFORM=xcb

			openroad -gui

			Then from the TCL commands console at the bottom of the OpenROAD GUI open your new design:
			read_db runs/RUN_.../final/odb/neorv32_verilog_wrapper.odb

			There in the tool you can proceed to the Display Control panel on the left to hide standard cells and inspect the routing layers.
			* Under the Visibility tab, uncheck Instances (or specifically StdCells) to hide the internal logic gates.
			* Expand the Layers menu. Here, you can toggle individual routing layers (met1, met2, met3, met4, met5) and vias to visually trace the physical connections across the die.

			To jump directly to the physical wires that caused the antenna failures:
			* In the top menu bar, navigate to Tools -> DRC Viewer.
			* Click Load and navigate to the antenna report generated during your run. This is typically located at:
			runs/RUN_.../reports/routing/antenna.rpt (or an equivalent .json or .lyrdb file in the signoff/routing reports directory).
			* The DRC Viewer will open a list of the violations, if any.
			* Click on any violation in the list. The main camera will instantly pan, zoom, and highlight the exact wire segment and layer where the charge accumulation risk occurs.

Leo: /* Expected results */

2026-06-19T17:05:40Z

Expected results

← Older revision		Revision as of 17:05, 19 June 2026
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	#** DRC (Design Rule Check): The geometry of your standard cells, power straps, and routing wires strictly obeys the Sky130 foundry's physical manufacturing rules (minimum spacing, width, etc.).		#** DRC (Design Rule Check): The geometry of your standard cells, power straps, and routing wires strictly obeys the Sky130 foundry's physical manufacturing rules (minimum spacing, width, etc.).
	#** LVS (Layout vs. Schematic): The final geometric layout perfectly matches your synthesized Verilog netlist. No unexpected shorts or open circuits were created during routing.		#** LVS (Layout vs. Schematic): The final geometric layout perfectly matches your synthesized Verilog netlist. No unexpected shorts or open circuits were created during routing.

	#. Antenna Violations (Failed 𐄂 - 8 Violations)		#. Antenna Violations (Failed 𐄂 - 8 Violations)
	#* During plasma etching in fabrication, long metal wires act like antennas, collecting electrostatic charge that can blow out the thin gate oxides of connected transistors.		#* During plasma etching in fabrication, long metal wires act like antennas, collecting electrostatic charge that can blow out the thin gate oxides of connected transistors.
	#* OpenLane attempted to fix these automatically (since we enabled RUN_ANTENNA_REPAIR), usually by jumping to higher metal layers or inserting "tie-down" diodes near the gates.		#* OpenLane attempted to fix these automatically (since we enabled RUN_ANTENNA_REPAIR), usually by jumping to higher metal layers or inserting "tie-down" diodes near the gates.
	#* 8 violations simply mean a few nets are still too long relative to their connected gate area. In a real tape-out, you would manually inspect these in the GUI and force diode insertion or add routing blockages.		#* 8 violations simply mean a few nets are still too long relative to their connected gate area. In a real tape-out, you would manually inspect these in the GUI and force diode insertion or add routing blockages.

	#. Max Slew & Max Cap Violations (Warnings)		#. Max Slew & Max Cap Violations (Warnings)
	#* These are electrical rule violations indicating that some signals are transitioning too slowly (slew) or driving too much load (capacitance).		#* These are electrical rule violations indicating that some signals are transitioning too slowly (slew) or driving too much load (capacitance).

Leo: /* config.json */

2026-06-19T17:05:19Z

config.json

← Older revision		Revision as of 17:05, 19 June 2026
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	}		}
	}		}

			==== Expected results ====
			If all goes well, after an hour or so you may see the final remarks of the design in the terminal before it finishes.
			A few important bits there:
			#. DRC & LVS (Passed ✅)
			#** DRC (Design Rule Check): The geometry of your standard cells, power straps, and routing wires strictly obeys the Sky130 foundry's physical manufacturing rules (minimum spacing, width, etc.).
			#** LVS (Layout vs. Schematic): The final geometric layout perfectly matches your synthesized Verilog netlist. No unexpected shorts or open circuits were created during routing.

			#. Antenna Violations (Failed 𐄂 - 8 Violations)
			#* During plasma etching in fabrication, long metal wires act like antennas, collecting electrostatic charge that can blow out the thin gate oxides of connected transistors.
			#* OpenLane attempted to fix these automatically (since we enabled RUN_ANTENNA_REPAIR), usually by jumping to higher metal layers or inserting "tie-down" diodes near the gates.
			#* 8 violations simply mean a few nets are still too long relative to their connected gate area. In a real tape-out, you would manually inspect these in the GUI and force diode insertion or add routing blockages.

			#. Max Slew & Max Cap Violations (Warnings)
			#* These are electrical rule violations indicating that some signals are transitioning too slowly (slew) or driving too much load (capacitance).
			#* Because we relied on OpenLane's generic fallback constraints rather than providing a custom .sdc (Synopsys Design Constraints) file, the timing-driven routing and buffer insertion heuristics were not strictly optimized for your specific 25ns clock period across all extreme temperature/voltage corners.
			#* For a functional test run, these are completely safe to ignore.

			Now it is time to look at the generated layout.

Leo: /* VHDL to Verilog */

2026-06-19T16:39:19Z

VHDL to Verilog

← Older revision		Revision as of 16:39, 19 June 2026
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	Install the ghdl for conversion unless already installed, and start the conversion process:		Install the ghdl for conversion unless already installed, and start the conversion process. Move the Verilog file to your project sourde directory when done:
	sudo apt-get install ghdl		sudo apt-get install ghdl
	make check		make check
	make convert		make convert
			mv src/neorv32_verilog_wrapper.v <your-project-dir>/src/


	==== config.json ====		==== config.json ====

Leo: /* config.json */

2026-06-19T16:36:35Z

config.json

← Older revision		Revision as of 16:36, 19 June 2026
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	"RUN_HEURISTIC_DIODE_INSERTION": true,		"RUN_HEURISTIC_DIODE_INSERTION": true,
	"RUN_LINTER": false,		"RUN_LINTER": false,


	"_comment":		"_comment":
	{		{