Template:DIP saites: Difference between revisions

From DiLab
Jump to navigation Jump to search
← Older edit
Content deleted Content added
 
(61 intermediate revisions by the same user not shown)
Line 1: Line 1:
= Termini =

* IC - Integrated Circuit - mikroshēma.
* FPGA - Field Programmable Gate Array - Konfigurējams loģisko un citu elementu čips, "lego" kluči digitālai elektronikai.
* EDA - Dizaina plūsma: Electronic Design Automation [https://en.wikipedia.org/wiki/Design_flow_(EDA) (wikipedia)]
* RTL - [https://en.wikipedia.org/wiki/Register-transfer_level Register-Transfer Level] - dizaina abstrakcija, kurā dati plūst starp reģistriem.
* [https://en.wikipedia.org/wiki/GDSII GDSII] - Binārs datubāzes falia formāts IC dizaina apmaiņai industrijā.

= Resursi =
= Resursi =


Line 36: Line 44:


* [http://www.xilinx.com Xilinx kompānijas (FPGA ražotājs) portāls]
* [http://www.xilinx.com Xilinx kompānijas (FPGA ražotājs) portāls]
* [http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf Spartan 3E FPGA Family datasheet]
<!-- * [http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf Spartan 3E FPGA Family datasheet] -->
* [https://datasheetspdf.com/pdf-file/1409860/Xilinx/XC3S500E/1 Spartan 3E FPGA Family datasheet]
* [https://www.xilinx.com/support/documentation/data_sheets/ds160.pdf Spartan-6 FPGA Family datasheet]
* [https://www.xilinx.com/support/documentation/application_notes/xapp462.pdf Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs]
* [https://www.xilinx.com/support/documentation/application_notes/xapp462.pdf Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs]


Line 43: Line 53:
DiLab ir pieejami sekojoši Xilinx (Digilent) attīstītajrīki:
DiLab ir pieejami sekojoši Xilinx (Digilent) attīstītajrīki:


* '''[https://reference.digilentinc.com/reference/programmable-logic/anvyl/start ANVYL]'''
* Spartan-3E
** Anvyl Reference Manual: [https://reference.digilentinc.com/_media/reference/programmable-logic/anvyl/anvyl_rm.pdf (PDF)] [https://digilent.com/reference/programmable-logic/anvyl/reference-manual (Website)]
** [[ANVYL programmēšana]] - Pamācība, kā uzlādēt dizainu uz Anvyl dēļa
** [https://github.com/elomage/FPGA-resources/tree/main/ucf_templates UCF file templates].

* '''[http://www.pynq.io/ PYNQ]''' [https://reference.digilentinc.com/reference/programmable-logic/pynq-z1/start -Z1]
** [https://www.digikey.com/en/articles/techzone/2019/apr/build-and-program-fpga-based-designs-quickly-python-jupyter-notebooks Build and Program FPGA-Based Designs Quickly with Python and Jupyter Notebooks] - with Zynq (PYNQ)

* '''[https://reference.digilentinc.com/reference/programmable-logic/spartan-3e/start Spartan-3E]'''
** [http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf Xilinx Spartan-3E FPGA Starter Kit Board User Guide] PDF 7.34MB
** [http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf Xilinx Spartan-3E FPGA Starter Kit Board User Guide] PDF 7.34MB
** [http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/spartan3e_scm.pdf Spartan-3E Libraries Guide for Schematic Designs] PDF 9.19MB
** [http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/spartan3e_scm.pdf Spartan-3E Libraries Guide for Schematic Designs] PDF 9.19MB
** [http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/spartan3e_hdl.pdf Spartan-3E Libraries Guide for HDL Designs] PDF 3.94MB
** [http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/spartan3e_hdl.pdf Spartan-3E Libraries Guide for HDL Designs] PDF 3.94MB
** [https://github.com/elomage/FPGA-resources/tree/main/ucf_templates UCF file templates].
** [https://reference.digilentinc.com/reference/programmable-logic/spartan-3e/start Spartan 3E rīka ražotāja references lapa]


* [http://www.xilinx.com/products/boards/s3e1600e/reference_designs.htm Spartan-1600e]
* [http://www.xilinx.com/products/boards/s3e1600e/reference_designs.htm Spartan-1600e]


* [http://www.xilinx.com/univ/xupv2p.html XUP V2P]
* [https://reference.digilentinc.com/reference/programmable-logic/virtex-ii-pro/start XUP V2P], no [http://www.xilinx.com/univ/xupv2p.html Xilinx University Program]


* [https://www.digikey.com/en/articles/techzone/2019/apr/build-and-program-fpga-based-designs-quickly-python-jupyter-notebooks Build and Program FPGA-Based Designs Quickly with Python and Jupyter Notebooks] - with Zynq (PYNQ)


==== PMOD papildus moduļi ====
==== PMOD papildus moduļi ====
Mums ir pieejami daži PMOD perifērijas iekārtu moduļi (pārsvarā 1x6 formātā) par kuriem sīkāk var lasīt [https://store.digilentinc.com/pmod-expansion-modules/by-form-factor/1x6/ Digilentic portālā].
Mums ir pieejami dažādi [https://reference.digilentinc.com/reference/pmod/start PMOD perifērijas iekārtu moduļi] (pārsvarā 1x6 formātā) par kuriem sīkāk var lasīt [https://store.digilentinc.com/pmod-expansion-modules/by-form-factor/1x6/ Digilentic portālā].
* ADC modulis [https://store.digilentinc.com/pmod-ad1-two-12-bit-a-d-inputs/ PmodAD1 PB200064]
* ADC modulis [https://store.digilentinc.com/pmod-ad1-two-12-bit-a-d-inputs/ PmodAD1 PB200064]
* DAC modulis: [https://store.digilentinc.com/pmod-da2-two-12-bit-d-a-outputs/ PmodDA2 PB200-113]
* DAC modulis: [https://store.digilentinc.com/pmod-da2-two-12-bit-d-a-outputs/ PmodDA2 PB200-113]
Line 70: Line 87:
* Skaļrunis ar 3.5mm konektoru: [https://store.digilentinc.com/speaker/ SPEAKER]
* Skaļrunis ar 3.5mm konektoru: [https://store.digilentinc.com/speaker/ SPEAKER]


* Konektors vadiem [https://reference.digilentinc.com/reference/pmod/pmodcon1/start PmodCON1]
=== Xilinx ISE WebPACK (14.7) ===
* Rotējošais enkoderis [https://reference.digilentinc.com/reference/pmod/pmodenc/start PmodENC]
* USB saskarne [https://reference.digilentinc.com/reference/pmod/pmodusbuart/start PmodUSBUART]
* Ultraskaņas distances mērītājs [https://reference.digilentinc.com/reference/pmod/pmodmaxsonar/start PmodMAXSONAR]
* Audio DAC SPI [https://reference.digilentinc.com/reference/pmod/pmodmic3/start PmodMIC3]


=== Xilinx ISE instalācija ===
Xilinx ISE Webpack versija 14.7 (Windows 7, nevis Windows 10) ir pēdējā versija, kas vēl atbalsta Spartan 3E FPGA.
==== Xilinx ISE WebPACK (14.7) ====


* [[ISE 14.7 instalācija]]
To iespējams lejuplādēt no [https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive-ise.html Xilinx arhīva web portāla], kurā nepieciešams šim nolūkam izveidot kontu.


<!--
* [[ISE WebPACK 14.7 USB driver]] instalācija
==== Xilinx ISE WebPACK (12.2) ====
Papildus:
* [https://www.xilinx.com/support/answers/59128.html Digilent driver installation] (no Xilinx portāla)
* [http://dreamrunner.org/blog/2012/09/12/install-xilinx-ise-on-the-ubuntu/ Install Xilinx ISE on Ubuntu] (learn&think)
* [https://www.george-smart.co.uk/fpga/xilinx_jtag_linux/ Install Linux ISE] (George Smart)

=== Xilinx ISE WebPACK (12.2) ===


* [https://secure.xilinx.com/webreg/register.do?group=dlc&htmlfile=&emailFile=&cancellink=&eFrom=&eSubject=&version=12.2&akdm=1&filename=Xilinx_ISE_DS_Lin_12.2_M.63c.1.1.tar Installer for Linux] TAR/GZ 3.02GB (nepieciešams reģistrēties www.xilinx.com)
* [https://secure.xilinx.com/webreg/register.do?group=dlc&htmlfile=&emailFile=&cancellink=&eFrom=&eSubject=&version=12.2&akdm=1&filename=Xilinx_ISE_DS_Lin_12.2_M.63c.1.1.tar Installer for Linux] TAR/GZ 3.02GB (nepieciešams reģistrēties www.xilinx.com)
Line 94: Line 111:
* [http://rmdir.de/~michael/xilinx/ Xilinx JTAG tools on Linux without proprietary kernel modules]
* [http://rmdir.de/~michael/xilinx/ Xilinx JTAG tools on Linux without proprietary kernel modules]


* [http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/ise_tutorial_ug695.pdf ISE In-Depth Tutorial] PDF 5.04MB
* [http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/ise_tutorial_ug695.pdf ISE In-Depth Tutorial] (ver.12.2) PDF 5.04MB
* [http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/plugin_ism.pdf ISim User Guide] (ver.12.2) PDF 1.96MB

< -->

=== Xilinx ISE lietošana ===
* [https://github.com/elomage/FPGA-resources/tree/main/ucf_templates UCF failu šabloni] FPGA platformām.

==== Vispārīga lietošana ====
* [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ise_tutorial_ug695.pdf ISE In-Depth Tutorial] (ver.14.7) PDF
* [https://www.xilinx.com/support/documentation-navigation/development-tools/hardware-development/ISE-design-suite.html?preSelect=documenttype:SeeAll#documentation Xilinx ISE dokumentācija] - dažādi dokumenti

==== Simulācija ar ISim ====

* [https://www.youtube.com/watch?v=9iQfqhUfAcE Kā lietot iSim] (video, Leo Seļāvo)
* [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/plugin_ism.pdf ISim User Guide] (ver.14.7) PDF 1.96MB
* [https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug682.pdf ISim in-depth Tutorial] PDF
<!-- * [https://youtu.be/hPYsQE0-1kQ Simulācija ar ISim] - pamācības video, Colin O'Flynn. -->


==== Simulācija ar ModelSim ====
* [http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/plugin_ism.pdf ISim User Guide] PDF 1.96MB
* [https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ise_tutorial_ug695.pdf Xilinx ISE In-Depth Tutorial] - PDF
* [https://www.cis.upenn.edu/~milom/cis371-Spring13/lab/simulation/ Pamācība no Pensilvānijas Universitātes]
* [https://youtu.be/DgRrATFd3jc How to do a Timing Simulation using Modelsim and Xilinx ISE] - video pamācība


=== Video applications using FPGA ===
=== Video applications using FPGA ===
Line 106: Line 143:
[https://store.digilentinc.com/anvyl-spartan-6-fpga-trainer-board/ ANVYL]
[https://store.digilentinc.com/anvyl-spartan-6-fpga-trainer-board/ ANVYL]
ir Xilinx Spartan 6G FPGA bāzēts attīstītājrīks ar dažādām papildus un perifērijas iekārtām.
ir Xilinx Spartan 6G FPGA bāzēts attīstītājrīks ar dažādām papildus un perifērijas iekārtām.

* [[ANVYL programmēšana]] - kā uzlādēt dizainu uz Anvyl dēļa
* [https://youtu.be/9iQfqhUfAcE Video ar Anvyl programmēšanas piemēru]


== PYNQ ietvars ==
== PYNQ ietvars ==
Line 121: Line 161:
* [https://github.com/drichmond/RISC-V-On-PYNQ RISC-V on PYNQ]
* [https://github.com/drichmond/RISC-V-On-PYNQ RISC-V on PYNQ]


PYNK un PMOD
== HDL tutorials ==
* [https://pynq.readthedocs.io/en/v2.0/pynq_libraries/pmod.html Par PMOD un PYNQ]

== HDL pamācības (Verilog, VHDL) ==


<!-- (unavailable) * [http://www.eecs.harvard.edu/cs141/resources/verilog-tutorial.pdf Verilog Tutorial I (10 pages)] PDF 69.58KB -->
<!-- (unavailable) * [http://www.eecs.harvard.edu/cs141/resources/verilog-tutorial.pdf Verilog Tutorial I (10 pages)] PDF 69.58KB -->
Line 130: Line 173:
** [http://www.asic-world.com/verilog/veritut.html by asic-world, online version]
** [http://www.asic-world.com/verilog/veritut.html by asic-world, online version]
** [https://www.nandland.com/verilog/tutorials/tutorial-introduction-to-verilog-for-beginners.html by NANDLand.com]
** [https://www.nandland.com/verilog/tutorials/tutorial-introduction-to-verilog-for-beginners.html by NANDLand.com]
** [https://www.asic-world.com/tidbits/verilog_fsm.html FSM pamācība] no asic-world.com


* '''VHDL Tutorials'''
* '''VHDL Tutorials'''
** [http://www.gmvhdl.com/VHDL.html VHDL Tutorial I (15 pages)]
** [http://www.gmvhdl.com/VHDL.html VHDL Tutorial I (15 pages)]
** [http://lslwww.epfl.ch/pages/teaching/cours_lsl/sl_info/vhdl-tutorial.pdf VHDL Tutorial II (84 pages)] PDF 391.95KB
** [http://lslwww.epfl.ch/pages/teaching/cours_lsl/sl_info/vhdl-tutorial.pdf VHDL Tutorial II (84 pages)] PDF 391.95KB

* Debouncing
** [https://www.fpga4student.com/2017/04/simple-debouncing-verilog-code-for.html Verilog code for debouncing buttons on FPGA]

== RISC-V ==

* [https://riscv.org/technical/specifications/ Specifications]
* [https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md Getting started] - Assembly manual
* [https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/RISCVGreenCardv8-20151013.pdf Green card]
* [https://five-embeddev.com/riscv-isa-manual/latest/instr-table.html RISC-V Instruction Set Manual] from five-embeddev.com
* [https://www.cs.cornell.edu/courses/cs3410/2019sp/riscv/interpreter/ RISC-V Interpretators online]
* [https://riscvasm.lucasteske.dev/# RISC-V Online Assembler]


== Seriālie protokoli ==
== Seriālie protokoli ==
Line 150: Line 206:
** [https://www.rfwireless-world.com/Tutorials/1-wire-protocol-basics.html 1-wire protocol basics] at rfwireless-world.com
** [https://www.rfwireless-world.com/Tutorials/1-wire-protocol-basics.html 1-wire protocol basics] at rfwireless-world.com
** [https://www.maximintegrated.com/en/design/technical-documents/tutorials/1/1796.html Guide to 1-wire devices] at Maxim-IC
** [https://www.maximintegrated.com/en/design/technical-documents/tutorials/1/1796.html Guide to 1-wire devices] at Maxim-IC

* USB
** [https://www.cypress.com/file/134171/download Specifikācija] - Infineon / Cypress.


== IP cores priekš FPGA ==
== IP cores priekš FPGA ==
Line 158: Line 217:
== Ieteikumi prezentāciju veidošanā ==
== Ieteikumi prezentāciju veidošanā ==
[http://andromeda.df.lu.lv/wiki/index.php/LU::poster-howto Piezīmes par plakātu un prezentāciju veidošanu]
[http://andromeda.df.lu.lv/wiki/index.php/LU::poster-howto Piezīmes par plakātu un prezentāciju veidošanu]

== Atsauksmes par kursu ==
* DIP 2012-1-m: [http://bit.ly/MVbhuZ] [http://bit.ly/Lvsur2] [http://bit.ly/MX4Upj]



== Citi kursi un saites ==
== Citi kursi un saites ==
* [http://www.ecs.umass.edu/ece/koren/architecture/ Computer architecture education tools] at UMass

* [https://8bitworkshop.com/ 8 Bit Workshop] - aparatūras simulators pārlūkā, tai skaitā Verilog.
* [https://8bitworkshop.com/ 8 Bit Workshop] - aparatūras simulators pārlūkā, tai skaitā Verilog.


Line 197: Line 254:


* [https://www.acm.org/hennessy-patterson-turing-lecture 2017 ACM A.M. Turing Award recipients John Hennessy and David Patterson delivered the Turing Lecture on June 4 at ISCA 2018]
* [https://www.acm.org/hennessy-patterson-turing-lecture 2017 ACM A.M. Turing Award recipients John Hennessy and David Patterson delivered the Turing Lecture on June 4 at ISCA 2018]

* [https://youtu.be/TPbroUDHG0s Spēļu programmēšana 8 bitu arhitektūrā]

* [https://youtu.be/V9xUQWo4vN0 Tranzistors] - 1953.gada dokumentālā filma


== FPGA pielietojumi ==
== FPGA pielietojumi ==
* [http://www.wired.com/2014/06/microsoft-fpga/ Microsoft Supercharges Bing Search With Programmable Chips]
* [http://www.wired.com/2014/06/microsoft-fpga/ Microsoft Supercharges Bing Search With Programmable Chips]
* [https://tang.sipeed.com/en/ Tang primer board] for RISC V
* [https://thedatabus.io/fpga-buying-guide FPGA buying guide]

Latest revision as of 10:28, 19 February 2026

Termini

  • IC - Integrated Circuit - mikroshēma.
  • FPGA - Field Programmable Gate Array - Konfigurējams loģisko un citu elementu čips, "lego" kluči digitālai elektronikai.
  • EDA - Dizaina plūsma: Electronic Design Automation (wikipedia)
  • RTL - Register-Transfer Level - dizaina abstrakcija, kurā dati plūst starp reģistriem.
  • GDSII - Binārs datubāzes falia formāts IC dizaina apmaiņai industrijā.

Resursi


Digital design textbooks @ Digilent Inc.

Saites

Xilinx produkti (FPGA čipi)

Xilinx attīstītajrīki

DiLab ir pieejami sekojoši Xilinx (Digilent) attīstītajrīki:


PMOD papildus moduļi

Mums ir pieejami dažādi PMOD perifērijas iekārtu moduļi (pārsvarā 1x6 formātā) par kuriem sīkāk var lasīt Digilentic portālā.

Xilinx ISE instalācija

Xilinx ISE WebPACK (14.7)


Xilinx ISE lietošana

Vispārīga lietošana

Simulācija ar ISim

Simulācija ar ModelSim

Video applications using FPGA

ANVYL attīstītājrīks

ANVYL ir Xilinx Spartan 6G FPGA bāzēts attīstītājrīks ar dažādām papildus un perifērijas iekārtām.

PYNQ ietvars

PYNQ ir ietvars kas iespējo FPGA aparatūras funkciju izmantošanu ar Python programmēšanas valodu. Atbalstītā aparatūra iekļauj ZYNQ.

PYNQ informācijas avoti:

PYNQ projekti

PYNK un PMOD

HDL pamācības (Verilog, VHDL)

RISC-V

Seriālie protokoli

IP cores priekš FPGA


Ieteikumi prezentāciju veidošanā

Piezīmes par plakātu un prezentāciju veidošanu

Citi kursi un saites

  • 8 Bit Workshop - aparatūras simulators pārlūkā, tai skaitā Verilog.

Domu graudi

FPGA pielietojumi

Retrieved from "https://andromeda.df.lu.lv/wiki/index.php?title=Template:DIP_saites&oldid=11205"