Difference between revisions of "Template:DIP saites"

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(Xilinx ISE WebPACK (14.7))
(HDL tutorials)
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* '''Verilog Tutorials'''
 
* '''Verilog Tutorials'''
** [http://users.ece.cmu.edu/~jhoe/course/ece447/handouts/LV.pdf by Peter
 Milder] handout (15 pages).
+
** [https://users.ece.cmu.edu/~jhoe/course/ece447/S09handouts/LV.pdf handout] by Peter
 Milder (15 pages).
 
** [http://www.ece.umd.edu/class/enee359a.S2008/verilog_tutorial.pdf by asic-world] (227 pages) PDF 876.25KB
 
** [http://www.ece.umd.edu/class/enee359a.S2008/verilog_tutorial.pdf by asic-world] (227 pages) PDF 876.25KB
 
** [http://www.asic-world.com/verilog/veritut.html by asic-world, online version]
 
** [http://www.asic-world.com/verilog/veritut.html by asic-world, online version]

Revision as of 12:12, 15 April 2017

Literatūra


Digital design textbooks @ Digilent Inc.

Saites

Xilinx produkti (FPGA čipi)

Xilinx attīstītajrīki

DiLab ir pieejami sekojoši Xilinx (Digilent) attīstītajrīki:


Xilinx ISE WebPACK (14.7)

Papildus:

Xilinx ISE WebPACK (12.2)

Video applications using FPGA

HDL tutorials

IP cores priekš FPGA


Ieteikumi prezentāciju veidošanā

Atsauksmes par kursu


Citi kursi un saites

Domu graudi

FPGA pielietojumi